David Lee Baldwin

US Patent:

43969917, Aug 2, 1983

Filed:

Apr 7, 1981

Appl. No.:

6/251805

Inventors:

David R. Baldwin - Phoenix AZ
Nicholas S. Lemak - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

G06F 1520
H03B 304

US Classification:

364736

Abstract:

A long term response enhancement for a digital phase-locked loop is implemented to provide a relatively minor change in the phase of the output signal over a relatively long period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur between successive input signals, producing an output signal when the two numbers agree. The present invention modifies the average count prior to comparison with the number of pulses counted from the occurrence of the last output signal, by adding a one or a zero to the average count, based upon comparison of the previous two averages present during the previous two cycles of the input signal with the current average, with either a one or a zero added to the comparison number, thereby providing for slight modification of the time at which the output signal would be produced.

US Patent:

44411952, Apr 3, 1984

Filed:

Jul 10, 1981

Appl. No.:

6/251846

Inventors:

David R. Baldwin - Phoenix AZ
Nicholas S. Lemak - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

H03L 718

US Classification:

377 2

Abstract:

A short term response enhancement for a digital phase-locked loop is implemented to provide a relatively major change in the phase of the output signal over a relatively short period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur, producing an output signal when the two numbers agree. The number of pulses which occur between successive cycles of the input signal are also compared against the previously determined average. A count which differs from the average count indicates a change in phase of the input signal. The present invention takes the absolute value of the measured error and, based upon the prior modification made during the previous two cycles of the input signal to the count sequence modifies the count sequence of the counter which is counting the number of pulses from the last output signal, by either adding one or subtracting one from the count sequence, thereby effecting a relatively major change in the phase of the output signal over a relatively short period of time.

US Patent:

44621108, Jul 24, 1984

Filed:

Apr 7, 1981

Appl. No.:

6/251845

Inventors:

David R. Baldwin - Phoenix AZ
Nicholas S. Lemak - Phoenix AZ

Assignee:

Honeywell Information Systems Inc. - Phoenix AZ

International Classification:

H03B 304

US Classification:

377 43

Abstract:

A phase-locked loop is implemented using strictly digital techniques. The average frequency of the input signal is first sampled by counting the number of pulses from a clock source which occur during a predetermined number of occurrences of the input signal. Thereafter, the number of pulses counted is divided by the number of cycles of the input signal which occurred during the counting period to determine an average number of pulses per input signal cycle. The number of pulses which occur between successive cycles of the input signal are then counted and compared against the previously determined average. A count which differs from the average indicates a change in phase of the input signal, and after appropriate weighting, is used to update the average to a new average. An output signal is produced when the number of pulses counted during a cycle of the input signal equals the average number of pulses determined to occur between successive cycles of the input signal.

US Patent:

59436360, Aug 24, 1999

Filed:

Jul 24, 1997

Appl. No.:

8/900245

Inventors:

David L. Baldwin - Glendale AZ
David A. Bailey - Glendale AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 1520
H04B 1008

US Classification:

702 85

Abstract:

A calibrate and run bias voltage control method for an optical delay system utilizing a plurality of voltage controlled switches which may experience bias drift wherein during calibration an output optical power error signal of the system is monitored while rapidly changing the bias voltages to the switches according to a desired algorithm and setting the bias voltages at a the level achieved when the output error signal falls below a predetermined tolerance level.

US Patent:

60187018, Jan 25, 2000

Filed:

Sep 2, 1997

Appl. No.:

8/921788

Inventors:

David L. Baldwin - Glendale AZ
David A. Bailey - Glendale AZ

Assignee:

Honeywell Inc

International Classification:

G06F 1520
H04B 1008

US Classification:

702 85

Abstract:

A method and apparatus for preventing false nulls in an optical delay line by causing the input optical beam to be frequency modulated or variably time delayed so that the components of the optical signal in the output cannot be of equal magnitude and of opposite phase.