David L Becker

US Patent:

6342165, Jan 29, 2002

Filed:

Jul 19, 2000

Appl. No.:

09/619101

Inventors:

Kevin G. Donohoe - Boise ID
David S. Becker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 213065

US Classification:

216 67, 216 13, 216 17, 216 41, 216 74, 216 79, 438710, 438715, 438723

Abstract:

A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF and CH F , delivered at flow rates on the order of between about 10 and 40 sccm for CHF and between about 10 and 40 sccm for CH F. Small quantities, on the order of 10 sccm or less, of other gases such as C HF and CF may be added. A variant of the inventive etch process employing only CHF during a second phase thereof may be useful in providing a âpunchâ or dimple at the contact bottom extending into the pristine substrate silicon under the BPSG and, optionally, other layers, and can be used to etch through both BPSG layers and nitride films to contact a word line (or the like) thereunder wherein the contact so formed has a reduced taper as it passes through the nitride film above the word line, resulting in a desirable, larger contact dimension. The system chamber temperature is defined and controlled at the roof over the wafer and the ring surrounding the wafer, the roof being held at a temperature of about 115Â C. to 150Â C.

US Patent:

6436844, Aug 20, 2002

Filed:

Aug 27, 2001

Appl. No.:

09/939905

Inventors:

David S. Becker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21461

US Classification:

438761

Abstract:

A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protect on and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

US Patent:

6451678, Sep 17, 2002

Filed:

Nov 27, 2000

Appl. No.:

09/724885

Inventors:

David S. Becker - Boise ID

Assignee:

Micron Technology, lnc. - Boise ID

International Classification:

H01L 213205

US Classification:

438585, 438586, 438703, 438584, 438592, 438783

Abstract:

A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

US Patent:

6492279, Dec 10, 2002

Filed:

Jan 27, 2000

Appl. No.:

09/492738

Inventors:

David S. Becker - Boise ID
Bradley J. Howard - Boise ID
Kevin G. Donohoe - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21302

US Classification:

438714, 438723, 438724

Abstract:

A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0. 3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas. Such plasma etching is conducted under conditions effective to produce at least that portion of the one feature pattern in the feature layer formed during the one etching segment to have a sidewall taper, if any, of less than or equal to 5Â and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Such value is determinable by scanning electron microscopy as an average maximum size of all surface discernible objects of the patterned masking layer as measured and averaged along any 0.

US Patent:

6610212, Aug 26, 2003

Filed:

Jan 29, 2002

Appl. No.:

10/060436

Inventors:

Kevin G. Donohoe - Boise ID
David S. Becker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 213065

US Classification:

216 67, 204169, 204170, 216 13, 216 17, 216 41, 216 74, 216 79, 438710, 438715, 438723, 361230, 361235

Abstract:

A plasma etch process for etching BPSG employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber, which includes a fluorine scavenger in the form of silicon. The two primary etchant gases are CHF and CH F , delivered at flow rates on the order of between about 10 and 40 sccm for CHF and between about 10 and 40 sccm for CH F. Small quantities, on the order of 10 sccm or less, of other gases such as C HF and CF may be added.

US Patent:

6759320, Jul 6, 2004

Filed:

Aug 28, 2002

Appl. No.:

10/233039

Inventors:

David S. Becker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438620

Abstract:

A method of forming a transistor for a semiconductor device from a semiconductor wafer comprises forming a first nitride layer over the front and back of the wafer, and forming a second nitride layer over the front and back of the wafer and over the first nitride layer. A first resist layer is formed over the front of the wafer and at least a portion of the second nitride layer over the front of the wafer is exposed. The first and second nitride layers are removed from the back of the wafer while, simultaneously, at least a portion of the exposed portion of the second nitride layer over the front of the wafer is removed. Next, a second layer of resist is formed leaving at least a portion of the first nitride layer exposed. Finally, the exposed portion of the first nitride layer is etched.

US Patent:

6784108, Aug 31, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/651871

Inventors:

Kevin G. Donohoe - Boise ID
David S. Becker - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21302

US Classification:

438706, 438710, 438712, 438714, 216 67

Abstract:

Etch profile control with pulsed gas flow and its applications to etching such as anisotropic etching of high aspect ratio features and etching of self-aligned contact structures in various processes. Pulsing can be applied according to this invention to the flow rate of a gas such as an etchant gas, a gas that leads to the deposition of a protective layer, a gas that modifies the deposition of a protective layer, and a gas that modifies etching.

US Patent:

6812154, Nov 2, 2004

Filed:

Oct 17, 2002

Appl. No.:

10/273851

Inventors:

David S. Becker - Boise ID
Bradley J. Howard - Boise ID
Kevin G. Donohoe - Boise ID

Assignee:

Micron Technology, INC - Boise ID

International Classification:

H01L 21302

US Classification:

438714, 438723, 438724

Abstract:

A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0. 3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas. Such plasma etching is conducted under conditions effective to produce at least that portion of the one feature pattern in the feature layer formed during the one etching segment to have a sidewall taper, if any, of less than or equal to 5Â and an organic masking layer top outer surface roughness proximate the feature pattern at a conclusion of the etching segment which is characterizable by an average value less than 100 Angstroms. Such value is determinable by scanning electron microscopy as an average maximum size of all surface discernible objects of the patterned masking layer as measured and averaged along any 0.