David S Bernstein

US Patent:

43947360, Jul 19, 1983

Filed:

Feb 11, 1980

Appl. No.:

6/120272

Inventors:

David H. Bernstein - Ashland MA
Richard A. Carberry - Cupertino CA
Michael B. Druke - Chelmsford MA
Ronald I. Gusowski - Westboro MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations.

US Patent:

44930232, Jan 8, 1985

Filed:

May 22, 1981

Appl. No.:

6/266403

Inventors:

Edward S. Gavrin - Lincoln MA
Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Michael S. Richmond - Pittsboro NC
Walter A. Wallach - Raleigh NC
Richard A. Belgard - Saratoga CA
David A. Farber - Durham NC
John K. Ahlstrom - Mountain View CA
Steven J. Wallach - Saratoga CA
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA
David H. Bernstein - Ashland MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 930

US Classification:

364200

Abstract:

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration.

US Patent:

40756920, Feb 21, 1978

Filed:

Nov 1, 1976

Appl. No.:

5/737416

Inventors:

Karsten Sorensen - Lexington MA
David H. Bernstein - Cambridge MA
Michael B. Druke - Cambridge MA

Assignee:

Data General Corporation - Southboro MA

International Classification:

G06F 738

US Classification:

364200

Abstract:

A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.

US Patent:

40140067, Mar 22, 1977

Filed:

Jan 2, 1976

Appl. No.:

5/646351

Inventors:

Karsten Sorensen - Lexington MA
David H. Bernstein - Cambridge MA
Michael B. Druke - Cambridge MA

Assignee:

Data General Corporation - Southboro MA

International Classification:

G06F 1300

US Classification:

3401725

Abstract:

A data processing system in which the central processor unit operates asynchronously with one or more memory units independently of the operating speed of the memory units wherein the central processor timing signal and the memory timing signal have a predetermined phase relationship. The central processor unit is arranged to remain operative even when the memory unit is enabled unless it is disabled by a signal from the memory unit under preselected conditions. The central processor generates a plurality of operating instruction signals for transfer to the memory unit to permit the latter to perform its desired functions by enabling the memory unit, inhibiting the transfer of data from the memory unit to a data bus and permitting storage of data from the central processor unit when data is acceptable for such storage. A further operating instruction signal is generated at the central processor unit to permit data read from the memory unit to be modified at the central processor unit and stored in the memory unit after such modification. A further operating instruction signal is generated internally to the memory unit to prevent operation of all other memory devices in the memory unit when one of the memory devices therein is in operation.

US Patent:

44981317, Feb 5, 1985

Filed:

May 22, 1981

Appl. No.:

6/266408

Inventors:

Richard G. Bratt - Wayland MA
Edward S. Gavrin - Lincoln MA
Stephen I. Schleimer - Chapel Hill NC
John F. Pilat - Raleigh NC
Walter A. Wallach - Raleigh NC
Michael S. Richmond - Pittsboro NC
Richard A. Belgard - Saratoga CA
David A. Farber - Durham NC
John K. Ahlstrom - Mountain View CA
Steven J. Wallach - Saratoga CA
Lawrence H. Katz - Oregon City OR
Douglas M. Wells - Chapel Hill NC
Craig J. Mundie - Cary NC
Gerald F. Clancy - Saratoga CA
David H. Bernstein - Ashland MA
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A digital data processing system has a memory organized into objects containing at least operands and instructions. Each object is identified by a unique and permanent identifier code which identifies the data processing system and the object. The system utilizes unique addressing mechanisms the addresses of which have object fields, offset fields and length fields for specifying the location and the total number of bits of an addressed object. The system uses a protection technique to prevent unauthorized access to objects by users who are identified by a subject number which identifies the user, a process of the system for executing the user's procedure, and the type of operation of the system to be performed by the user's procedure. An access control list for each object includes an access control list entry for each subject having access rights to the object and means for confirming that a particular active subject has access rights to a particular object before permitting access to the object.

US Patent:

45325863, Jul 30, 1985

Filed:

May 22, 1981

Appl. No.:

6/266401

Inventors:

Richard G. Bratt - Wayland MA
Stephen I. Schleimer - Chapel Hill NC
Edward S. Gavrin - Lincoln MA
John F. Pilat - Raleigh NC
Steven J. Wallach - Saratoga CA
Lawrence H. Katz - Oregon City OR
Douglas M. Wells - Chapel Hill NC
Gerald F. Clancy - Saratoga CA
Craig J. Mundie - Cary NC
David H. Bernstein - Ashland MA
Thomas M. Jones - Chapel Hill NC
Brett L. Bachman - Boston MA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A digital computer system in which data storage is referred to by a descriptor comprising an object number denoting a variable-length block of storage, an offset indicating how far into that block a desired data item begins, and a length field denoting the length of the desired data item. Separate means exist for manipulating each of the three descriptor portions, thus facilitating repetitive operations on related or contiguous operands. Various levels of microcode control are included. Each level of microcode control has its own stack, facilitating interrupts between levels. Stacks are duplicated in "secure stacks" in memory to protect against loss of state data from the stacks.

US Patent:

44803060, Oct 30, 1984

Filed:

May 22, 1981

Appl. No.:

6/266425

Inventors:

Brett L. Bachman - Boston MA
Richard A. Belgard - Saratoga CA
David H. Bernstein - Ashland MA
Richard G. Bratt - Wayland MA
Gerald F. Clancy - Saratoga CA
Edward S. Gavrin - Lincoln MA
Thomas M. Jones - Chapel Hill NC
Lawrence H. Katz - Oregon City OR
Craig J. Mundie - Cary NC
John F. Pilat - Raleigh NC
Stephen I. Schleimer - Chapel Hill NC
Steven J. Wallach - Saratoga CA
Walter A. Wallach - Raleigh NC
Douglas M. Wells - Chapel Hill NC

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 922

US Classification:

364200

Abstract:

A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration and, as particularly described with reference to the invention herein, identify locations of object information to be accessed by utlizing address formats which comprise an object field, offset field and a length field so that information can be identified to bit granular level and to information type and format.

US Patent:

44995350, Feb 12, 1985

Filed:

May 22, 1981

Appl. No.:

6/266427

Inventors:

Brett L. Bachman - Boston MA
Richard A. Belgard - Saratoga CA
David H. Bernstein - Ashland MA
Richard G. Bratt - Wayland MA
Gerald F. Clancy - Saratoga CA
Edward S. Gavrin - Lincoln MA
Ronald H. Gruner - Cary NC
Thomas M. Jones - Chapel Hill NC
Craig J. Mundie - Cary NC
James T. Nealon - Cary NC
John F. Pilat - Raleigh NC
Stephen I. Schleimer - Chapel Hill NC
Steven J. Wallach - Saratoga CA

Assignee:

Data General Corporation - Westboro MA

International Classification:

G06F 934
G06F 704

US Classification:

364200

Abstract:

A digital computer uses a memory which is structured into objects, which are blocks of storage of arbitrary length, in which data items are accessed by descriptors which for a desired data item specify the object, the offset into that object, and the length of the data object. The computer system of the present invention further provides the ability to execute any of a plurality of dialects of internal instructions, the repertoire of such dialects being virtually infinite, since there is the ability to load a supporting microcode during operation as needed.