David M Biven

US Patent:

20040098699, May 20, 2004

Filed:

Nov 14, 2002

Appl. No.:

10/295301

Inventors:

Frank Breejen - Tucson AZ, US
David Biven - Austin TX, US
William Torke - Cedar Creek TX, US
William Gardei - Derry NH, US

Assignee:

Cirrus Logic, Incorporated - Austin TX

International Classification:

G06F017/50

US Classification:

716/015000

Abstract:

An integrated circuit, in which one or more internal parameters may be automatically configured for a particular application, includes a plurality of program select pins, each being in a predetermined fixed state, and at least one configuration pin associated with a parameter to be adjusted. Jumpers on the system board to which the integrated circuit is mounted connect the mounting pad of each configuration pin with the mounting pad of a selected program select pin. Consequently, when the integrated circuit is mounted on the system board, each configuration pin receives a selected value which internal configuration circuitry detects and causes the corresponding parameter to be adjusted accordingly. Any of the program select pins may have functions in addition to the configuration function. When the system board is powered on or undergoes a reset, a processor internal to the chip scans each the configuration pin to determine its value. The processor then sets internal registers accordingly, completing the configuration process, and the chip may begin normal operation.

US Patent:

20210082811, Mar 18, 2021

Filed:

Feb 12, 2019

Appl. No.:

16/954430

Inventors:

Scott WARRICK - Austin TX, US
- Edinburgh, GB
Eric J. KING - Austin TX, US
John L. MELANSON - Austin TX, US
Anthony S. DOY - Boulder CO, US
David M. BIVEN - Austin TX, US

Assignee:

Cirrus Logic International Semiconductor Ltd. - Edinburgh

International Classification:

H01L 23/522
H01L 23/31
H01L 23/00

Abstract:

A method for fabricating an integrated circuit upon a substrate may include forming a passive electrical component in a non-final layer of the integrated circuit and forming one or more electrical contacts in a final layer of the integrated circuit such that the one or more electrical contacts and the passive electrical component are positioned in a manner such that an imaginary line perpendicular to and from a surface of the substrate intersects the passive electrical component and the one or more electrical contacts.