David C Briggs

US Patent:

6432753, Aug 13, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/840246

Inventors:

Buddhika J. Abesingha - Plano TX
Gabriel A. Rincon-Mora - Allen TX
David D. Briggs - Richardson TX
Roy Alan Hastings - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438127, 438106

Abstract:

A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

US Patent:

6661216, Dec 9, 2003

Filed:

Aug 26, 2002

Appl. No.:

10/227942

Inventors:

David A. Grant - Dallas TX
David D. Briggs - Richardson TX
Ayesha I. Mayhugh - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 158

US Classification:

323282, 323285, 323901

Abstract:

An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.

US Patent:

6709900, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166964

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21332

US Classification:

438140, 438141, 438454

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

6710427, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/167136

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Chin-Yu Tsai - HsinChu Seien, TW
David D. Briggs - Richardson TX
Dale Skelton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257549, 257502, 257500, 257544

Abstract:

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased.

US Patent:

6734705, May 11, 2004

Filed:

Aug 12, 2002

Appl. No.:

10/217249

Inventors:

Mark Pulkin - Rowlett TX
David D. Briggs - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19175

US Classification:

326 68, 326 62, 326 83, 327333, 327371

Abstract:

The low voltage to high voltage level shifter has falling-edge 1-shot circuits and coupled to the outputs OUT and OUT_B of cross gate-connected transistors and and pull-down transistors and. The falling-edge 1-shot circuits and output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop. The flip flop provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.

US Patent:

6750553, Jun 15, 2004

Filed:

Aug 9, 2001

Appl. No.:

09/925983

Inventors:

Buddhika J. Abesingha - Plano TX
Gabriel A. Rincon-Mora - Allen TX
David D. Briggs - Richardson TX
Roy Alan Hastings - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2328

US Classification:

257787, 257678, 257795

Abstract:

A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

US Patent:

6784493, Aug 31, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166956

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257347, 257502, 257549

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

20130033903, Feb 7, 2013

Filed:

Aug 4, 2012

Appl. No.:

13/567039

Inventors:

Ross E. Teggatz - McKinney TX, US
David Briggs - McKinney TX, US
Amer H. Atrash - Dallas TX, US
Wayne T. Chen - Plano TX, US

Assignee:

TRIUNE IP LLC - Richardson TX

International Classification:

H02M 3/24

US Classification:

363 16

Abstract:

Disclosed are advances in the arts with novel and useful current mode regulators. Circuits, systems, and methods for current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.