David A Briggs

US Patent:

6432753, Aug 13, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/840246

Inventors:

Buddhika J. Abesingha - Plano TX
Gabriel A. Rincon-Mora - Allen TX
David D. Briggs - Richardson TX
Roy Alan Hastings - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438127, 438106

Abstract:

A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

US Patent:

6709900, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166964

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21332

US Classification:

438140, 438141, 438454

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

6710427, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/167136

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Chin-Yu Tsai - HsinChu Seien, TW
David D. Briggs - Richardson TX
Dale Skelton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257549, 257502, 257500, 257544

Abstract:

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased.

US Patent:

6750553, Jun 15, 2004

Filed:

Aug 9, 2001

Appl. No.:

09/925983

Inventors:

Buddhika J. Abesingha - Plano TX
Gabriel A. Rincon-Mora - Allen TX
David D. Briggs - Richardson TX
Roy Alan Hastings - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2328

US Classification:

257787, 257678, 257795

Abstract:

A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

US Patent:

6784493, Aug 31, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166956

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257347, 257502, 257549

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

20130033903, Feb 7, 2013

Filed:

Aug 4, 2012

Appl. No.:

13/567039

Inventors:

Ross E. Teggatz - McKinney TX, US
David Briggs - McKinney TX, US
Amer H. Atrash - Dallas TX, US
Wayne T. Chen - Plano TX, US

Assignee:

TRIUNE IP LLC - Richardson TX

International Classification:

H02M 3/24

US Classification:

363 16

Abstract:

Disclosed are advances in the arts with novel and useful current mode regulators. Circuits, systems, and methods for current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.

US Patent:

55370675, Jul 16, 1996

Filed:

Mar 11, 1994

Appl. No.:

8/209858

Inventors:

Fernando D. Carvajal - McKinney TX
David D. Briggs - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 100

US Classification:

327108

Abstract:

A signal driver circuit (10) is provided that comprises a first inverter comprising a P-FET (14), an N-FET (16) and a resistor (18). A second inverter comprises a P-FET (20) and an N-FET (22). Resistor (18) and capacitors (24) and (26) limit the transition times of the output driving signal to control electromagnetic radiation caused by rapid transition times in the output signal. Circuit (10) is independent of the amount of capacitive load (28) driven by the circuit.

US Patent:

6140683, Oct 31, 2000

Filed:

Feb 16, 1999

Appl. No.:

9/251015

Inventors:

Charvaka Duvvury - Plano TX
David Douglas Briggs - Dallas TX
Fernando David Carvajal - McKinney TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2362

US Classification:

257360

Abstract:

A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.