David A Briggs

US Patent:

6661216, Dec 9, 2003

Filed:

Aug 26, 2002

Appl. No.:

10/227942

Inventors:

David A. Grant - Dallas TX
David D. Briggs - Richardson TX
Ayesha I. Mayhugh - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 158

US Classification:

323282, 323285, 323901

Abstract:

An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.

US Patent:

6709900, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166964

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21332

US Classification:

438140, 438141, 438454

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

6710427, Mar 23, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/167136

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Chin-Yu Tsai - HsinChu Seien, TW
David D. Briggs - Richardson TX
Dale Skelton - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257549, 257502, 257500, 257544

Abstract:

A distributed power device ( ) including a plurality of tank regions ( ) separated from one another by a deep n-type region ( ), and having formed in each tank region a plurality of transistors ( ). The plurality of transistors ( ) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D ) is defined from each tank region to a buried layer, and a second parasitic diode (D ) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer ( ) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D ) between the NBL layer and the substrate will never be forward biased.

US Patent:

6784493, Aug 31, 2004

Filed:

Jun 11, 2002

Appl. No.:

10/166956

Inventors:

Taylor R. Efland - Richardson TX
David A. Grant - Dallas TX
Ramanathan Ramani - Richardson TX
Dale Skelton - Plano TX
David D. Briggs - Richardson TX
Chin-Yu Tsai - HsinChu Hsien, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2900

US Classification:

257347, 257502, 257549

Abstract:

A power integrated circuit architecture ( ) having a high side transistor ( ) interposed between a control circuit ( ) and a low side transistor ( ) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region ( ) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring ( ) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays ( ) partitioned by at least one deep n-type region ( ), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.

US Patent:

60878525, Jul 11, 2000

Filed:

Dec 8, 1998

Appl. No.:

9/206871

Inventors:

David D. Briggs - Dallas TX
Fernando D. Carvajal - McKinney TX
Chao-Chih Chiu - Taipei, TW

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 190175
H03L 500

US Classification:

326 68

Abstract:

The invention is a multiplex circuit for outputing two or more signals of different levels to a common output pad where a first output driver (D. sub. h) is powered from a voltage rail having a higher voltage than at least one second output driver (D. sub. 1) power by a lower voltage rail. An interface circuit (IFC) and level shift circuit provides two output signals base on a single input signal, one signal being equivalent to the voltage of the higher voltage (V. sub. High) and the other being based on the lower voltage (V. sub. low). PMOS device connected to the output pad has its back gate connected to V. sub. high to prevent leakage current through the PMOS device when the output to the output pad (P. sub. 1) is equivalent to V. sub. High.