David C Burden

US Patent:

6484301, Nov 19, 2002

Filed:

May 25, 2001

Appl. No.:

09/865268

Inventors:

David C Burden - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 8, 716 15, 716 19

Abstract:

The present invention includes a system for and a method of identifying the location of contact pads on interconnect layers of printed circuit boards or metal layers of integrated circuits. The invention groups the conductive surfaces into rectangular areas and applies a mask to the identified rectangular areas by aligning a corner of the mask with the corresponding corner of the rectangular area. Once aligned, the remaining corners of the mask are checked to see whether there is an underlying conductive material present at all corners thereby identifying a suitable location for a contact pad. The invention further includes an alignment of alternate corners of the mask with the corresponding corner of the rectangular area if previous attempts to identify a contact pad were unsuccessful.

US Patent:

6691285, Feb 10, 2004

Filed:

Aug 27, 2002

Appl. No.:

10/229535

Inventors:

David C. Burden - Fort Collins CO
Dave Anderson - Fort Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1750

US Classification:

716 2, 716 4, 716 5, 716 6, 716 7, 716 8, 716 9, 716 10

Abstract:

A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.

US Patent:

6862715, Mar 1, 2005

Filed:

Jul 29, 2002

Appl. No.:

10/207578

Inventors:

David C. Burden - Fort Collins CO, US
Matthew Biggi - Fort Collins CO, US
Jaime Weisberg - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 2

Abstract:

A process is shown for determining crossover current in a circuit design. One or more static CMOS gates are identified within the circuit design. One or more widths of at least one of a P-stack and N-stack associated with the CMOS gates are then determined. A voltage slope at the input of, and a capacitive load at the output of, one or more of the nodes are also determined. Crossover current, per static CMOS gate, is estimated based on the widths, the voltage slope and capacitive load. An overall crossover current is determined by summing individual gate-level crossover currents. The circuit design may be optimized for power consumption, for example, by modifying design elements of the circuit design while monitoring overall crossover current.

US Patent:

6892374, May 10, 2005

Filed:

Jun 19, 2002

Appl. No.:

10/174674

Inventors:

Bruno P. Melli - Windsor CO, US
David C. Burden - Fort Collins CO, US
Matthew L. Biggio - Fort Collins CO, US

International Classification:

G06F017/50

US Classification:

716 19, 716 9, 716 10

Abstract:

In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.

US Patent:

6904573, Jun 7, 2005

Filed:

May 27, 2003

Appl. No.:

10/446097

Inventors:

David Burden - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F017/50

US Classification:

716 2, 716 6

Abstract:

Techniques are disclosed for estimating the signal propagation delays within a circuit, based on a description of the circuit written in a hardware description language (HDL), such as a register transfer language (RTL). Assignment statements in the description which describe the performance of a logical function are modeled using logic gates which perform the function described. A particular function may be modeled using one or more logic gates depending on the number of inputs to the function. The delay associated with performance of the function is estimated by estimating the delay through the circuit used to model the function. Estimates for multiple functions may be combined to estimate the total delay associated with a particular signal path through a circuit.

US Patent:

7000204, Feb 14, 2006

Filed:

Sep 2, 2003

Appl. No.:

10/653650

Inventors:

Tyson R. McGuffin - Fort Collins CO, US
Thomas W. Chen - Fort Collins CO, US
David C. Burden - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 17/50

US Classification:

716 5, 716 18

Abstract:

Systems and methods are provided that can be utilized to estimate power associated with a circuit design. The estimated power is determined by employing power characterizations associated with dynamic and static power related parameters of a circuit design. The power characterizations can be determined prior to circuit design optimizations, stored and utilized during circuit design optimizations.

US Patent:

20040019473, Jan 29, 2004

Filed:

Jul 24, 2002

Appl. No.:

10/205332

Inventors:

David Burden - Fort Collins CO, US
Tyson McGuffin - Fort Collins CO, US

International Classification:

G06F017/50

US Classification:

703/014000

Abstract:

A process for processing a circuit design. One or more critical design paths of the circuit design are determined. These paths may for example be determined relative to timing and/or current utilization. Design elements of the paths may be grouped by type (e.g., FETs, wires). The circuit design may be optimized by processing a reduced set of design elements as determined by the critical paths and grouping. Optimization may include modifying FET design element width, or a routing path of a wire design element, along a critical path of the design, and comparing the new optimization relative to preselected design goals such as timing and power consumption.

US Patent:

20050021238, Jan 27, 2005

Filed:

Jul 21, 2003

Appl. No.:

10/624266

Inventors:

Tyson McGuffin - Fort Collins CO, US
Thomas Chen - Fort Collins CO, US
Dave Anderson - Fort Collins CO, US
David Burden - Fort Collins CO, US

International Classification:

G06F019/00
G01N033/48
G01N033/50

US Classification:

702020000

Abstract:

The convergence speed of a computer-implemented genetic optimization process is improved through the correction of child chromosomes containing undesirable gene combinations. Undesirable gene combinations may be identified through application of heuristic techniques, statistical techniques, or a combination of the two.