David J Carlson

Address:

13483 S Warner Way, Riverton, UT 84065

VIN:

3VWRW31C47M521355

Make:

VOLKSWAGEN

Model:

NEW BEETLE

Year:

2007

US Patent:

7558925, Jul 7, 2009

Filed:

Jan 18, 2006

Appl. No.:

11/335189

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

G06F 12/02

US Classification:

711154, 711104

Abstract:

Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i. e. , read) more often than they are stored (i. e. , written).

US Patent:

7594081, Sep 22, 2009

Filed:

Dec 28, 2004

Appl. No.:

11/024002

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711138

Abstract:

A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.

US Patent:

8301788, Oct 30, 2012

Filed:

Sep 7, 2005

Appl. No.:

11/220899

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/16
G06F 15/173
H04L 12/28
H04J 3/06

US Classification:

709230, 709208, 709221, 709231, 709246, 370389, 370392, 370503

Abstract:

A computer-readable instruction is described for traversing deterministic finite automata (DFA) graphs to perform a pattern search in the in-coming packet data in real-time. The instruction includes one or more pre-defined fields. One of the fields includes a DFA graph identifier for identifying one of several previously-stored DFA graphs. Another one of the fields includes an input reference for identifying input data to be processed using the identified DFA graphs. Yet another one of the fields includes an output reference for storing results generated responsive to the processed input data. The instructions are forwarded to a DFA engine adapted to process the input data using the identified DFA graph and to provide results as instructed by the output reference.

US Patent:

8392590, Mar 5, 2013

Filed:

Sep 7, 2005

Appl. No.:

11/221408

Inventors:

Gregg A. Bouchard - Round Rock TX, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US
Muhammad R. Hussain - Pleasanton CA, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 15/16
G06F 17/28

US Classification:

709230, 704 2

Abstract:

A processor for traversing deterministic finite automata (DFA) graphs with incoming packet data in real-time. The processor includes at least one processor core and a DFA module operating asynchronous to the at least one processor core for traversing at least one DFA graph stored in a non-cache memory with packet data stored in a cache-coherent memory.

US Patent:

20060223084, Oct 5, 2006

Filed:

Dec 5, 2005

Appl. No.:

11/293577

Inventors:

David Carlson - Austin TX, US

International Classification:

C12Q 1/68
C12P 19/34

US Classification:

435006000, 435091200

Abstract:

The present invention relates to methods, compositions, and kits for detecting the presence of and binding partners to . The invention also relates to polynucleotide sequences that are specific for the genome and proteins encoded by those sequences.