David C Carlson

US Patent:

6434586, Aug 13, 2002

Filed:

Jan 29, 1999

Appl. No.:

09/240419

Inventors:

David Albert Carlson - Hudson MA
Derek Scott Brasili - Fitchburg MA
Vishnu V. Yalala - Shrewsbury MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 752

US Classification:

708625, 708627, 708632

Abstract:

A multiplier including a processor that generates at least one N by M array of partial products. The processor includes a first section that performs a first operation that generates an N by M array of partial products representing low order bits, and a second section that performs a second operation that generates an N by M array of partial products representing high order bits. The multiplier also includes a compressor that compresses the N by M array of partial products representing low order bits after the first operation and generates a plurality of carry bits that are utilized in the second operation. The multiplier further includes a memory for saving the plurality of carry bits generated by the compressor; a feedback mechanism that recirculates the plurality of carry bits obtained from the memory and utilizes the plurality of carry bits for calculations performed in the second operation; and an adder that separately sums the N by M array of partial products representing low order bits and the N by M array of partial products representing high order bits. In one embodiment, the multiplier includes a Wallace multiplier. The invention also relates to a method of electronically multiplying an N bit multiplicand by an M bit multiplier using a P bit Wallace multiplier.

US Patent:

6789147, Sep 7, 2004

Filed:

Dec 19, 2001

Appl. No.:

10/025512

Inventors:

Richard E. Kessler - Shrewsbury MA
David A. Carlson - Haslet TX
Muhammad Raghib Hussain - Pleasanton CA
Robert A. Sanzone - Hudson MA
Khaja E. Ahmed - Pleasanton CA
Michael D. Varga - Milpitas CA

Assignee:

Cavium Networks - Santa Clara CA

International Classification:

G06F 900

US Classification:

710200, 713200, 712 34

Abstract:

A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.

US Patent:

7240203, Jul 3, 2007

Filed:

Dec 19, 2001

Appl. No.:

10/025509

Inventors:

Richard E. Kessler - Shrewsbury MA, US
David A. Carlson - Haslet TX, US
Muhammad Raghib Hussain - Pleasanton CA, US
Robert A. Sanzone - Hudson MA, US
Khaja E. Ahmed - Pleasanton CA, US
Michael D. Varga - Milpitas CA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

H04L 9/00

US Classification:

713171

Abstract:

A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of output data structures associated with the number of requests within a remote memory based on pointers stored in the number of requests. The number of execution units can output the results in an order that is different from the order of the requests in a request queue. The processor also includes a request unit coupled to the number of execution units. The request unit is to retrieve a portion of the number of requests from the request queue within the remote memory and associated input data structures for the portion of the number of requests from the remote memory. Additionally, the request unit is to distribute the retrieved requests to the number of execution units based on availability for processing by the number of execution units.

US Patent:

7941585, May 10, 2011

Filed:

Dec 17, 2004

Appl. No.:

11/015343

Inventors:

David H. Asher - Sutton MA, US
David A. Carlson - Haslet TX, US
Richard E. Kessler - Shrewsbury MA, US

Assignee:

Cavium Networks, Inc. - Mountain View CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711101, 711129, 711130, 711E12001, 711E12046

Abstract:

A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.

US Patent:

20060059286, Mar 16, 2006

Filed:

Jan 25, 2005

Appl. No.:

11/042476

Inventors:

Michael Bertone - Marlborough MA, US
David Carlson - Haslet TX, US
Richard Kessler - Shrewsbury MA, US
Philip Dickinson - Cupertino CA, US
Muhammad Hussain - Pleasanton CA, US
Trent Parker - San Jose CA, US

Assignee:

Cavium Networks - Santa Clara CA

International Classification:

G06F 13/24

US Classification:

710260000

Abstract:

In a multi-core processor, a high-speed interrupt-signal interconnect allows more than one of the processors to be interrupted at substantially the same time. For example, a global signal interconnect is coupled to each of the multiple processors, each processor being configured to selectively provide an interrupt signal, or pulse thereon. Preferably, each of the processor cores is capable of pulsing the global signal interconnect during every clock cycle to minimize delay between a triggering event and its respective interrupt signal. Each of the multiple processors also senses, or samples the global signal interconnect, preferably during the same cycle within which the pulse was provided, to determine the existence of an interrupt signal. Upon sensing an interrupt signal, each of the multiple processors responds to it substantially simultaneously. For example, an interrupt signal sampled by each of the multiple processors causes each processor to invoke a debug handler routine.

US Patent:

20120216050, Aug 23, 2012

Filed:

Feb 23, 2012

Appl. No.:

13/403360

Inventors:

Craig Barner - Shrewsbury MA, US
David Carlson - Haslet TX, US

Assignee:

Cavium, Inc. - San Jose CA

International Classification:

G06F 21/00

US Classification:

713189

Abstract:

A microcode authentication unit provides access to a secure hardware unit. A microcode segment is provided to the microcode authentication unit, which generates a signature corresponding to the segment and compares the size and signature of the segment against stored values. If a match is determined, the unit enables access to the secure hardware unit.

US Patent:

63177722, Nov 13, 2001

Filed:

Jan 19, 1999

Appl. No.:

9/234021

Inventors:

David A. Carlson - Hudson MA

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 750

US Classification:

708655

Abstract:

The invention provides computer apparatus for performing a division operation having a dividend mathematically divided by a divisor. The dividend and the divisor are split between a state machine and an array of carry save adders. The most significant bits of the dividend and the divisor are input to the state machine and the least significant bits of the dividend and the divisor are input to the carry save adder array. The state machine is fully encoded with partial remainder values and quotient digit values for all possible combinations of the most significant bits of the divisor and the dividend. The carry save adders add the respective least significant bits of the dividend and the divisor and output spillover signals to the state machine. The state machine provides partial remainders and quotient digits selected from the encoded partial remainder values and quotient digit values dependent on (i. e. as a function of) the most significant bits of the dividend, divisor and the spillover signals.

US Patent:

40090310, Feb 22, 1977

Filed:

Jun 6, 1975

Appl. No.:

5/584488

Inventors:

David P. Carlson - Westboro MA
Thomas R. Keenan - Reading MA
Douglas L. Marks - Burlington MA

Assignee:

Polaroid Corporation - Cambridge MA

International Classification:

G03C 554
G03C 700
G03C 140
B44D 109

US Classification:

96 29D

Abstract:

Coating a solution comprising a hydrophilic colloid and ammonia over a receiving layer comprising polyvinylpyridine in an image-receiving element of a photographic film unit significantly reduces haze and facilitates the separation of the image-receiving element from the remainder of the film unit subsequent to diffusion transfer processing.