David Michael Carson

Address:

10054 Solid Lime St, Las Vegas, NV 89183

VIN:

5TENX22N57Z426704

Make:

TOYOTA

Model:

TACOMA

Year:

2007

US Patent:

59110511, Jun 8, 1999

Filed:

Sep 27, 1996

Appl. No.:

8/721686

Inventors:

David G. Carson - Portland OR
George R. Hayek - Cameron Park CA
Brent S. Baxter - Hillsboro OR
Colyn Case - Grass Valley CA
Kim A. Meinerth - Granite Bay CA
Brian K. Langendorf - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1314

US Classification:

395287

Abstract:

A high throughput memory access interface is provided. The interface includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The interface allows memory access requests to be performed in such a manner that only portions of an access request are required to be transmitted to the target device for certain bus transactions. Each access request includes command bits, address bits, and length bits. In the initiating device, each access request is separated into three segments, which are stored in separate registers in both the initiating device and the target device. Only the segment which contains the lowest order address bits and the length bits is required by the target device to initiate the bus transaction. Thus, if either of the other two segments has not changed since the previous access request, then such segment or segments are not transmitted to the target.

US Patent:

44738803, Sep 25, 1984

Filed:

Jan 26, 1982

Appl. No.:

6/342837

Inventors:

David L. Budde - Portland OR
David G. Carson - Hillsboro OR
Stephen R. Colley - San Jose CA
David B. Johnson - Portland OR
Robert P. Voll - Portland OR
Doran K. Wilde - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300
H04J 600

US Classification:

364200

Abstract:

An arbitration mechanism comprising a request FIFO (408) for storing ones and zeros corresponding to received requests in the order that they are made. A one indicates that the request was made by the module in which the FIFO is located, and a zero indicates that the request was made by one of a number of other similar modules. The request status information from the other modules is received over signal lines (411) connected between the modules. This logic separates multiple requests into time-ordered slots, such that all requests in a particular time slot may be serviced before any requests in the next time slot. A store (409) stores a unique logical module number. An arbiter (410) examines this logical number bit-by-bit in successive cycles and places a one in a grant queue (412) upon the condition that the bit examined in a particular cycle is a zero and signals this condition over the signal lines. If the bit examined in a particular cycle is a one, the arbiter drops out of contention and signals this condition over the signal lines (411). This logic orders multiple requests within a single time slot, which requests are made by multiple modules, in accordance with the logical module numbers of the modules making the requests.

US Patent:

45035350, Mar 5, 1985

Filed:

Jun 30, 1982

Appl. No.:

6/393906

Inventors:

David L. Budde - Portland OR
David G. Carson - Hillsboro OR
Anthony L. Cornish - Essex, GB2
David B. Johnson - Portland OR
Craig B. Peterson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1100

US Classification:

371 11

Abstract:

A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area. Logic in the node reconfigures at least part of the system upon the condition that the node ID in the error report message identifies the node as a node which is part of a confinement area which should be recofigured to recover from the error reported in the error report message.

US Patent:

63178036, Nov 13, 2001

Filed:

Sep 27, 1996

Appl. No.:

8/721893

Inventors:

Norman J. Rasmussen - Hillsboro OR
Gary A. Solomon - Hillsboro OR
David G. Carson - Portland OR
George R. Hayek - Cameron Park CA
Brent S. Baxter - Hillsboro OR
Colyn Case - Grass Valley CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710107

Abstract:

A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible using standard local bus architectures, such as PCI or ISA. The port allows memory read and write requests to be pipelined in order to hide the effects of memory access latency. In particular, the port allows bus transactions to be performed in either a non-pipelined mode, such as provided by PCI, or in a pipelined mode. In the pipelined mode, one or more additional memory access requests are permitted to be inserted between a first memory access request and its corresponding data transfer. In contrast, in the non-pipelined mode, an additional memory access request cannot be inserted between a first memory access request and its corresponding data transfer.

US Patent:

54107105, Apr 25, 1995

Filed:

Dec 30, 1993

Appl. No.:

8/176136

Inventors:

Nitin V. Sarangdhar - Beaverton OR
Dave Papworth - Beaverton OR
P. K. Nizar - El Dorado Hills CA
David G. Carson - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1326
G06F 1318

US Classification:

395725

Abstract:

A multiprocessor programmable interrupt controller system, for use in a multiprocessor system in which one processor unit is a functional redundant checking (FRC) unit, has a synchronous interrupt bus, distinct from the system (memory) bus, with an interrupt bus clock that has a frequency that is a subharmonic of the FRC unit master CPU clock, for handling interrupt request (IRQ) related messages and maintaining synchronism between the master and checker CPUs of the FRC unit. Additional embodiments provide for the use of D-type flip-flop synchronizers to accommodate FRC units whose internal (core) clock or external bus clock are not harmonically related to the interrupt clock frequency. Each processor unit has an interrupt acceptance unit (IAU) coupled to the interrupt bus for the acceptance of IRQs and for broadcasting of IRQs generated by its associated on-chip processor. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated IRQs.

US Patent:

52839044, Feb 1, 1994

Filed:

Jan 22, 1993

Appl. No.:

8/008074

Inventors:

David G. Carson - Hillsboro OR
Herman D. D'Hooge - Hillsboro OR
Kevin C. Kahn - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1326

US Classification:

395725

Abstract:

A multi-processor programmable interrupt controller system which includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.

US Patent:

44803079, Oct 30, 1984

Filed:

Jan 4, 1982

Appl. No.:

6/336866

Inventors:

David L. Budde - Portland OR
David G. Carson - Hillsboro OR
David B. Johnson - Portland OR
Doran K. Wilde - Aloha OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A number of intelligent bus interface units (100) are provided in a matrix of orthogonal lines interconnecting processor modules (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding control lines; and memory buses (107) with corresponding control lines (108). At the intersection of these lines is a bus interface unit node (100). The bus interface units function to pass memory requests from a processor module to a memory module attached to an MCU node and to pass any data associated with the requests. The memory bus is a packet-oriented bus. Accesses are handled by means of a series of messages transmitted by message generator (417) in accordance with a specific control protocol. Packets comprising one or more bus transmission slots are issued sequentially and contiguously. Each slot in a packet includes an opcode, address, data, control, and parity-check bits.

US Patent:

48294250, May 9, 1989

Filed:

Mar 1, 1988

Appl. No.:

7/168635

Inventors:

William L. Bain - Beaverton OR
David G. Carson - Hillsboro OR
George W. Cox - Portland OR
Robert C. Duzett - Hillsboro OR
Brad W. Hosler - Portland OR
Scott A. Ogilvie - Salt Lake City UT
Craig B. Peterson - Portland OR
John L. Wipfli - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 940
G06F 900

US Classification:

364200

Abstract:

An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers.