David M Choi

US Patent:

20060193174, Aug 31, 2006

Filed:

Feb 25, 2005

Appl. No.:

11/067313

Inventors:

David Choi - Cupertino CA, US
Eui Kwon - San Jose CA, US
Kyu Choi - Cupertino CA, US

Assignee:

O2IC - Santa Clara CA

International Classification:

G11C 11/34
G11C 14/00

US Classification:

365185080

Abstract:

A memory cell structure includes non-volatile as well as SRAM memory cells that share the same bitline and operate differentially. The SRAM cell includes first and second MOS transistors that are coupled to the same true and complementary bit lines that the non-volatile memory cells are coupled to. The non-volatile memory cells are erased prior to being programmed. Programming of the non-volatile memory cells may be carried out via hot-electron injection or Fowler-Nordheim tunneling. Data stored in the non-volatile memory cells may be transferred to the SRAM cell. The differential reading and writing of data reduces over-erase of the non-volatile devices.

US Patent:

20060227605, Oct 12, 2006

Filed:

Jan 3, 2006

Appl. No.:

11/325224

Inventors:

David Choi - Cupertino CA, US
John Villasenor - San Francisco CA, US

International Classification:

G11C 14/00

US Classification:

365185080

Abstract:

Architectures are described that can include integrated non-volatile memory modules. Integrated non-volatile memory modules are a form of memory that is integrated on a single chip and includes at least one volatile memory cell and at least one non-volatile memory device. Information can be loaded between the at least one memory cell and the at least one non-volatile memory device in coordination with the supply of power to the integrated non-volatile memory device. In many embodiments, the supply of power to the integrated non-volatile memory device and the loading of information between the volatile memory cells and non-volatile memory devices are controlled to conserve energy. One embodiment of the present invention includes processing circuitry connected to an integrated non-volatile memory module and a power supply connected to the processing circuitry and integrated non-volatile memory module. In addition, the integrated non-volatile memory module is integrated on a single chip and includes at least one volatile memory cell that is connected to at least one non-volatile memory device.

US Patent:

20070242514, Oct 18, 2007

Filed:

Mar 10, 2006

Appl. No.:

11/373818

Inventors:

David Choi - Cupertino CA, US
Kyu Choi - Cupertino CA, US

Assignee:

O2IC, Inc. - Santa Clara CA

International Classification:

G11C 11/34

US Classification:

365185170

Abstract:

A multitude of NAND flash memory cells coupled to a bit line of a NAND flash memory array includes, in part, a highly doped source region coupled to a first terminal and a highly doped drain region coupled to a second terminal of the multitude of cells. Each NAND memory cell includes, in part, a first gate layer and a second gate layer both adapted to receive a voltage. The second gate layers of the NAND flash memory cells are connected to one another.

US Patent:

20080061355, Mar 13, 2008

Filed:

Mar 1, 2007

Appl. No.:

11/713780

Inventors:

David Choi - Cupertino CA, US

Assignee:

Embedded Memory, Inc. - Cupertino CA
Ace Memory, Inc. - Santa Clara CA

International Classification:

H01L 29/788
H01L 21/336

US Classification:

257316000, 438266000, 257E29300, 257E21422

Abstract:

In accordance with the present invention, a new method, its structure and manufacturing method is described to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.

US Patent:

20080061358, Mar 13, 2008

Filed:

Mar 1, 2007

Appl. No.:

11/713548

Inventors:

David Choi - Cupertino CA, US

Assignee:

Embedded Memory, Inc. - Santa Clara CA

International Classification:

H01L 27/108
H01L 21/8242

US Classification:

257319000, 438266000, 257E27084, 257E21646

Abstract:

In accordance with the present invention, a new method, its structure and manufacturing method is proposed to reduce memory cell size about the half of the conventional method for a non-volatile NAND Flash cell. The control gates in a string of the NAND Flash cell array is formed as the combination of the drawn control gate and the self-aligned control gate by using a spacer method. The source and drain of a NAND cell is defined as the low doped region underneath the spacer.

US Patent:

20130107744, May 2, 2013

Filed:

Dec 13, 2012

Appl. No.:

13/714079

Inventors:

VENTURI WIRELESS, INC. - Milpitas CA, US
Krishna RAMADAS - Cupertino CA, US
Chico JAYANTHAN - San Ramon CA, US
David CHOI - Cupertino CA, US

Assignee:

VENTURI WIRELESS, INC. - Milpitas CA

International Classification:

H04W 24/02

US Classification:

370252

Abstract:

A system for optimizing communications on a radio network by altering transitions between different link states that includes several modules. The activity, environment, and load module monitor monitors the link layer based on spectral-load metrics and radio-link metrics. The state transition control module determines when user equipment transitions between different states based on the type of user equipment, user equipment battery life, whether the user equipment is connected to an alternating current outlet, a spectral cost, and a backhaul cost. The channel state influencer module uses any of direct messages, ping messages, and keep-alive messages to influence the link state. The policy and preference handler enables or disables transitions based on the bearer technology type, the type of user equipment, the user's subscription plan, and the load level on the network.

US Patent:

20180349218, Dec 6, 2018

Filed:

Jul 12, 2017

Appl. No.:

15/648416

Inventors:

- Cupertino CA, US
Eisuke Arai - San Jose CA, US
Amit K. Vyas - San Jose CA, US
David S. Choi - Cupertino CA, US
Franco Travostino - San Jose CA, US
Abhinav Pathak - Campbell CA, US
Daniel Lertpratchya - Campbell CA, US
Albert Liu - Sunnyvale CA, US
Anand Ramadurai - Los Gatos CA, US
Olivier Mardinian - Sunnyvale CA, US
Vividh Siddha - Sunnyvale CA, US

International Classification:

G06F 11/07

Abstract:

Some embodiments of the invention provide a novel architecture for debugging devices. This architecture includes numerous devices that without user intervention automatically detect and report bug events to a set of servers that aggregate and process the bug events. When a device detects a potential bug event, the device in some embodiments generates a description of the potential bug event, and sends the generated description to the server set through a network. In addition to generating such a description, the device in some embodiments directs one or more of its modules to gather and store a collection of one or more data sets that are relevant to the potential bug event, in case the event has to be further analyzed by the server set. In the discussion below, the generated bug-event description is referred to as the event signature, while the gathered collection of data sets for an event is referred to as the event's data archive. The server set aggregates and processes the bug-event signatures that it receives from the various devices. For only a subset of the reported bug-event signatures, the server set then directs the devices that sent these signatures to also send the data archives that these devices have gathered and stored for the events associated with these signatures. These data archives can be further analyzed to identify the root causes of the bug events.

US Patent:

20180349219, Dec 6, 2018

Filed:

Jul 12, 2017

Appl. No.:

15/648427

Inventors:

- Cupertino CA, US
Eisuke Arai - San Jose CA, US
Amit K. Vyas - San Jose CA, US
David S. Choi - Cupertino CA, US
Franco Travostino - San Jose CA, US
Abhinav Pathak - Campbell CA, US
Daniel Lertpratchya - Campbell CA, US
Albert Liu - Sunnyvale CA, US
Anand Ramadurai - Los Gatos CA, US
Olivier Mardinian - Sunnyvale CA, US
Vividh Siddha - Sunnyvale CA, US

International Classification:

G06F 11/07

Abstract:

Some embodiments of the invention provide a novel architecture for debugging devices. This architecture includes numerous devices that without user intervention automatically detect and report bug events to a set of servers that aggregate and process the bug events. When a device detects a potential bug event, the device in some embodiments generates a description of the potential bug event, and sends the generated description to the server set through a network. In addition to generating such a description, the device in some embodiments directs one or more of its modules to gather and store a collection of one or more data sets that are relevant to the potential bug event, in case the event has to be further analyzed by the server set. In the discussion below, the generated bug-event description is referred to as the event signature, while the gathered collection of data sets for an event is referred to as the event's data archive. The server set aggregates and processes the bug-event signatures that it receives from the various devices. For only a subset of the reported bug-event signatures, the server set then directs the devices that sent these signatures to also send the data archives that these devices have gathered and stored for the events associated with these signatures. These data archives can be further analyzed to identify the root causes of the bug events.