David J Clinton

US Patent:

7110358, Sep 19, 2006

Filed:

May 26, 2000

Appl. No.:

09/580532

Inventors:

David Joseph Clinton - Germantown MD, US
Jonathan David Loewen - Belcarra, CA
Jeff Dillabough - Belcarra, CA
Minette Ashley Dannhardt - Vienna VA, US

Assignee:

PMC-Sierra, Inc. - Burnaby

International Classification:

G06F 11/00
H04L 12/28

US Classification:

370235, 370329, 3703954, 709224

Abstract:

A method or system or apparatus provides improved digital communication. In one aspect, destination scheduling is performed by scheduling polling rather than scheduling data emissions. In particular aspects, a loop port scheduler assigns a weight and sequence number to each destination and scheduling polling of ports using these parameters.

US Patent:

8271700, Sep 18, 2012

Filed:

Jan 24, 2011

Appl. No.:

13/012296

Inventors:

Babysaroja Annem - Allentown PA, US
David J. Clinton - Coopersburg PA, US
Praveen Alexander - Royersford PA, US

Assignee:

PMC-Sierra US, Inc. - Sunnyvale CA

International Classification:

G06F 13/28

US Classification:

710 26, 710 22

Abstract:

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function from logical address to physical address while supporting frequent context switching among a large number of logical address spaces. Embodiments of the present invention utilize per direction (source-destination) queuing and an internal switch to support non-blocking concurrent transfer of data on multiple directions. A caching technique can be incorporated to reduce the overhead of address translation.

US Patent:

8495301, Jul 23, 2013

Filed:

Nov 3, 2010

Appl. No.:

12/939128

Inventors:

Praveen Alexander - Royersford PA, US
Cheng Yi - Vancouver CA, US
Tao Zhong - Coquitlam CA, US
David J. Clinton - Coopersburg PA, US
Gary Nichols - Auburn CA, US

Assignee:

PMC-Sierra US, Inc. - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

711118, 711154, 710 22, 710 23, 710 26

Abstract:

A scatter gather cache system and method are provided, which increase performance of scatter-gather DMA operations by reducing the time taken by the DMA engine to perform a logical to physical address translation. This is done primarily by two-dimensional caching of scatter-gather elements of selected scatter-gather lists using a novel indexing, line swapping and replacement methodology. The cache can also include a context victim table (CVT) for storing scatter-gather list contexts from evicted cache entries and also allows for pre-fetching of SGL elements from Scatter-Gather Lists (SGL). It also provides coherency support when there are multiple instances of the cache accessing the same memory space.

US Patent:

20170177061, Jun 22, 2017

Filed:

Dec 17, 2015

Appl. No.:

14/972246

Inventors:

- Sunnyvale CA, US
Janardan PRASAD - Burnaby, CA
David Joseph CLINTON - Coopersburg PA, US

International Classification:

G06F 1/32

Abstract:

A power-saving method and circuit in a data processing device comprising a data buffer. Read commands associated with a data source and a data destination are received at the data processing device. The read commands are accumulated until an amount of read data associated with the read commands is greater than a predefined threshold. When the amount of read data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a sleep mode. When the amount of read data is at least the predefined threshold, the data buffer is signaled to exit the sleep mode following a preconfigured delay. Processing of the read commands and read data in respective pipelines is monitored to time exiting of the buffer from the sleep mode for arrival of the read data. Sleep mode use and thus power saving are optimized.