David B Connell

US Patent:

20010049593, Dec 6, 2001

Filed:

Feb 13, 2001

Appl. No.:

09/782589

Inventors:

David Mc Connell - Alameda CA, US
Ajithkumar Dasari - Santa Clara CA, US
Martin Mason - San Jose CA, US

International Classification:

G06F009/455
G06F017/50

US Classification:

703/014000

Abstract:

A method and system for co-verifying a hardware simulation of a field-programmable-system-level integrated circuit (FPSLIC) and a software simulation of the field-programmable-system-level integrated circuit. A FPSLIC device is simulated in hardware, and a simulator-port layout of the FPSLIC device is generated. In software, the method separately simulates, with an instruction-set simulator, the FPSLIC device, and outputs register contents from the instruction-set software. The contents from the simulator-port layout are verified with the register contents. Additionally, the method may further include outputting peripheral contents from the instruction-set simulator, and verifying contents from the simulator-port layout with the peripheral contents. UART contents also may be outputted from the instruction-set simulator, and verified with contents from the simulator-port layout with the UART contents.