David J Curry

US Patent:

6449741, Sep 10, 2002

Filed:

Oct 30, 1998

Appl. No.:

09/183038

Inventors:

Donald V. Organ - Saratoga CA
Kenneth J. Lanier - Medway MA
Roger W. Blethen - Dover MA
H. Neil Kelly - Westwood MA
Michael G. Davis - San Jose CA
Jeffrey H. Perkins - Cambridge MA
Tommie Berry - Pleasanton CA
Phillip Burlison - Morgan Hill CA
Mark Deome - San Jose CA
Christopher J. Hannaford - South Weymouth MA
Edward J. Terrenzi - Walpole MA
David Menis - Cohasset MA
David W. Curry - Cohasset MA
Eric Rosenfeld - Ashland MA

Assignee:

LTX Corporation - Westwood MA

International Classification:

H02H 305

US Classification:

714724, 714 46

Abstract:

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals.

US Patent:

6987732, Jan 17, 2006

Filed:

Dec 15, 2000

Appl. No.:

09/737917

Inventors:

Glenn Gracon - Palo Alto CA, US
Murray Bowles - Santa Clara CA, US
Kenneth C. Hsu - San Jose CA, US
David Curry - San Jose CA, US

Assignee:

Tellabs San Jose, Inc. - San Jose CA

International Classification:

G01R 31/08

US Classification:

3702351, 370231

Abstract:

A packet scheduler includes a packet manager interface, a policer, a congestion manager, a scheduler, and a virtual output queue (VOQ) handler. The policer assigns a priority to each packet. Depending on congestion levels, the congestion manager determines whether to send a packet based on the packet's priority assigned by the policer. The scheduler schedules packets in accordance with configured rates for virtual connections and group shapers. A scheduled packet is queued at a virtual output queue (VOQ) by the VOQ handler. In one embodiment, the VOQ handler sends signals to a packet manager (through the packet manager interface) to instruct the packet manager to transmit packets in a scheduled order.

US Patent:

7191368, Mar 13, 2007

Filed:

Aug 22, 2001

Appl. No.:

09/938157

Inventors:

Donald V. Organ - Saratoga CA, US
Kenneth J. Lanier - Medway MA, US
Roger W. Blethen - Dover MA, US
H. Neil Kelly - Westwood MA, US
Michael G. Davis - San Jose CA, US
Jeffrey H. Perkins - Cambridge MA, US
Tommie Berry - Pleasanton CA, US
Phillip Burlison - Morgan Hill CA, US
Mark Deome - San Jose CA, US
Christopher J. Hannaford - South Weymouth MA, US
Edward J. Terrenzi - Walpole MA, US
David Menis - Cohasset MA, US
David W. Curry - Cohasset MA, US
Eric Rosenfeld - Ashland MA, US

Assignee:

LTX Corporation - Norwood MA

International Classification:

G06F 11/00

US Classification:

714 57, 714 46, 715761, 715762, 715763, 715764, 715765

Abstract:

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals.

US Patent:

7614165, Nov 10, 2009

Filed:

Apr 22, 2005

Appl. No.:

10/568021

Inventors:

David R. Curry - Chicago IL, US

Assignee:

Podi, L.L.C. - Chicago IL

International Classification:

A43B 3/24

US Classification:

36101

Abstract:

Embodiments provide for an easily interchangeable footwear component, such as an upper portion of an article of footwear. In one embodiment, an article of footwear can comprise a fixed upper portion of an article of footwear, a sole fixedly connected to the fixed upper portion, and an interchangeable upper portion. Both the sole and the interchangeable upper portion can include one or more releasable fasteners, which allow the interchangeable upper portion to be releasably fastened to the article of footwear.

US Patent:

7639685, Dec 29, 2009

Filed:

Nov 22, 2006

Appl. No.:

11/603932

Inventors:

Vivek Venkatraman - Santa Clara CA, US
Ajay Virginkar - Fremont CA, US
Sanjay Khanna - Fremont CA, US
Balaji Rajagopalan - Sunnyvale CA, US
David S. Curry - San Jose CA, US

Assignee:

Tellabs San Jose, Inc. - Naperville IL

International Classification:

H04L 12/56
H04J 1/16

US Classification:

370390, 370412, 370419

Abstract:

A method or corresponding apparatus in an exemplary embodiment of the present invention determines how many copies of a multicast packet are to be sent, as copies, to multiple destinations based on information in the multicast packet and a group (e. g. , bridge node) with which the packet is associated. The copies of the multicast packets are then generated. After generating the copies, an action to take for each copy is determined. This determination is made using the information in the multicast packet and based on the group with which the packet is associated. After the action is determined for each copy, the action is performed on each copy. Through use of an embodiment of the present invention, memory space is conserved, allowing for continued use of a device in a multicast environment of an ever growing network, such as the Internet.

US Patent:

7697430, Apr 13, 2010

Filed:

Aug 29, 2005

Appl. No.:

11/215606

Inventors:

Glenn Gracon - Palo Alto CA, US
Murray Bowles - Santa Clara CA, US
Kenneth C. Hsu - San Jose CA, US
David Curry - San Jose CA, US

Assignee:

Tellabs San Jose, Inc. - San Jose CA

International Classification:

H04L 12/26

US Classification:

370232, 370235

Abstract:

A packet scheduler includes a packet manager interface, a policer, a congestion manager, a scheduler, and a virtual output queue (VOQ) handler. The policer assigns a priority to each packet. Depending on congestion levels, the congestion manager determines whether to send a packet based on the packet's priority assigned by the policer. The scheduler schedules packets in accordance with configured rates for virtual connections and group shapers. A scheduled packet is queued at a virtual output queue (VOQ) by the VOQ handler. In one embodiment, the VOQ handler sends signals to a packet manager (through the packet manager interface) to instruct the packet manager to transmit packets in a scheduled order.

US Patent:

8223642, Jul 17, 2012

Filed:

Apr 28, 2006

Appl. No.:

11/413409

Inventors:

David S. Curry - San Jose CA, US
Robert J. Colvin - San Jose CA, US
Samer I. Nubani - Santa Clara CA, US
Ravindra Sunkad - Pleasanton CA, US
Man-Tung T. Hsiao - Cupertino CA, US
Paul M. Hallinan - San Carlos CA, US
Rishi Mehta - San Jose CA, US
Sanjay Khanna - Fremont CA, US

Assignee:

Tellabs San Jose, Inc. - San Jose CA

International Classification:

H04L 12/56

US Classification:

370235, 3703954, 370412, 709234

Abstract:

Differentiated services for network traffic using weighted quality of service is provided. Network traffic is queued into separate per flow queues, and traffic is scheduled from the per flow queues into a group queue. Congestion management is performed on traffic in the group queue. Traffic is marked with priority values, and congestion management is performed based on the priority values. For example, traffic can be marked as “in contract” if it is within a contractual limit, and marked as “out of contract” if it is not within the contractual limit. Marking can also include classifying incoming traffic based on Differentiated Service Code Point. Higher priority traffic can be scheduled from the per flow queues in a strict priority over lower priority traffic. The lower priority traffic can be scheduled in a round robin manner.

US Patent:

20070208894, Sep 6, 2007

Filed:

Mar 27, 2006

Appl. No.:

11/390488

Inventors:

David Curry - San Jose CA, US
Bruce McLoughlin - Santa Clara CA, US
Ramkumar Krishnamoorthy - Cupertino CA, US

International Classification:

G06F 13/42

US Classification:

710105000

Abstract:

A method of modifying a layered protocol communication apparatus includes transferring a control plane from a first processor handling a first layer to a second processor handling a second layer.