David S Dunn

Address:

5300 Red Glory Dr, Las Vegas, NV 89130

Phone:

7024338599

VIN:

1GCHK23657F521988

Make:

CHEVROLET

Model:

SILVERADO 2500HD

Year:

2007

US Patent:

6421635, Jul 16, 2002

Filed:

Nov 2, 1998

Appl. No.:

09/184845

Inventors:

Bharath Chandramohan - San Clara CA
Rupert Brauch - Palo Alto CA
David A. Dunn - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 945

US Classification:

703 26, 703 23

Abstract:

The invention determines whether any asynchronous signals are pending and then delivers any such pending signals to the emulated application before the control is transferred to the operating system. A first mechanism sets a global flag, and checks to determine if any signals are pending. If there are pending signals, the emulator halts the emulation of the system call, and delivers the signal to the emulated application. A second mechanism handles signals that arrive after the first mechanism has performed its check. This mechanism checks to see if the global flag is set when a signal arrives. If the flag is set, then the signal is delivered immediately. If the flag is not set, then the signal is deferred. A third mechanism establishes a watch state at the beginning of the emulation, which would be changed by any action of the operating system. When a signal comes in, the emulator checks the watch state.

US Patent:

6526572, Feb 25, 2003

Filed:

Feb 9, 2000

Appl. No.:

09/500518

Inventors:

Rupert Brauch - San Jose CA
David A. Dunn - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06I 945

US Classification:

717154, 717131, 717152, 717153, 712226, 712227

Abstract:

The inventive mechanism operates to optimize program efficiency in a two phase process. In the first phase, the mechanism conducts a dependency analysis on the instructions to determine dependency relationships between the various instructions in an instruction window. The mechanism thereby identifies candidates for register renaming and instruction speculation, and provisionally performs the renaming and speculation operations, while preserving information which is preferably used to reverse these operations in the second phase if it is determined that the operations may be effectively rescheduled. In the second phase, the mechanism determines whether the optimizing operations, renaming and speculation, were beneficial in each case. Each instruction for which the mechanism finds the optimizing operation to be beneficial will generally remain in optimized form. Optimizing operations found not be beneficial are generally reversed by the mechanism.

US Patent:

6725361, Apr 20, 2004

Filed:

Jun 16, 2000

Appl. No.:

09/595199

Inventors:

Guillermo Rozas - Los Gatos CA
David Dunn - San Jose CA
David Dobrikin - Sunnyvale CA
Alex Klaiber - Mountain View CA
Daniel H. Nelsen - San Jose CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 1500

US Classification:

712222, 712202

Abstract:

A floating point processor including a plurality of explicitly-addressable processor registers, an emulation register capable of storing a value used to logically rename the explicitly-addressable registers to emulate registers of a floating point stack, a computer-executable software process for calculating and changing a value in the emulation register to a value indicating a change in addresses of registers of a floating point stack when executing a floating point stack operation, and adder circuitry combining a register address and the value in the emulation register in response to the computer-executable process to rename the plurality of explicitly-addressable processor registers.

US Patent:

6826682, Nov 30, 2004

Filed:

Jun 26, 2000

Appl. No.:

09/603743

Inventors:

Guillermo J. Rozas - Los Gatos CA
David Dunn - San Jose CA
Robert Cmelik - Sunnyvale CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 1107

US Classification:

712244, 703 27, 712222, 712227

Abstract:

A process which automatically inserts commands that test for raised exceptions indicating floating point status exceptions into a sequence of instructions to be executed, and responds to exceptions in execution of the sequence of instructions by returning execution to a point in the sequence of instructions at which correct state is known and then executing each instructions in the sequence singly to completion so that exceptions in pipelined floating point instructions can be automatically detected.

US Patent:

7062631, Jun 13, 2006

Filed:

Jul 17, 2003

Appl. No.:

10/623021

Inventors:

Alexander C. Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711207, 711141, 711154

Abstract:

A method and system for enforcing consistent per-physical page cacheability attributes is disclosed. The method for enforcing consistent per-physical page cacheability attributes maintains memory coherency within a processor addressing memory, such as by comparing a desired cacheability attribute of a physical page address in a PTE against an authoritative table that indicates the current cacheability status. This comparison can be made at the time the PTE is inserted into a TLB. When the comparison detects a mismatch between the desired cacheability attribute of the page and the page's current cacheability status, corrective action can be taken to transition the page into the desired cacheability state.

US Patent:

7149851, Dec 12, 2006

Filed:

Aug 21, 2003

Appl. No.:

10/646461

Inventors:

Guillermo Rozas - Los Gatos CA, US
Alexander Klaiber - Mountain View CA, US
David Dunn - Sammamish WA, US
Paul Serris - San Jose CA, US
Lacky Shah - Fremont CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 12/16

US Classification:

711141

Abstract:

Method and system for conservatively managing store capacity available to a processor issuing stores are provided and described. In particular, a counter mechanism is utilized, whereas the counter mechanism is incremented or decremented based on the occurrence of particular events.

US Patent:

7149872, Dec 12, 2006

Filed:

Jul 28, 2003

Appl. No.:

10/629031

Inventors:

Guillermo Rozas - Los Gatos CA, US
Alexander Klaiber - Mountain View CA, US
H. Peter Anvin - San Jose CA, US
David Dunn - Sammamish WA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711202, 711205

Abstract:

A system and method for identifying a TLB entry having a physical address that is within a specified range are disclosed. The method includes obtaining a tentative TLB entry from a page table entry and accessing a physical address associated with the tentative TLB entry. The method further includes comparing the physical address of the tentative TLB entry with a predetermined range of addresses. If the physical address is within the finite range of addresses, an exception is invoked. In response to the exception, the physical address and/or an attribute of the tentative TLB entry can be modified. The tentative TLB entry can then be stored in a TLB.

US Patent:

7225299, May 29, 2007

Filed:

Jul 16, 2003

Appl. No.:

10/622028

Inventors:

Guillermo Rozas - Los Gatos CA, US
Alexander Klaiber - Mtn. View CA, US
David Dunn - Sammamish WA, US
Paul Serris - Sunnyvale CA, US
Lacky Shah - Fremont CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 12/08

US Classification:

711144, 711137

Abstract:

Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality of states includes a speculative state to enable keeping track of speculative modification to data in the respective cache line. The speculative state enables a speculative modification to the data in the respective cache line to be made permanent in response to a first operation performed upon reaching a particular instruction boundary during speculative execution of instructions. Further, the speculative state enables the speculative modification to the data in the respective cache line to be undone in response to a second operation performed upon failing to reach the particular instruction boundary during speculative execution of instructions.