David Daniel Eaton

US Patent:

6426649, Jul 30, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751440

Inventors:

Robert Fu - Cupertino CA
David D. Eaton - San Jose CA
Kevin K. Yee - San Jose CA
Andrew K. Chan - Palo Alto CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H03K 738

US Classification:

326 41, 326 40, 326 39, 326 38, 326 86, 327293, 327292

Abstract:

A field programmable gate array includes a programmable interconnect structure and plurality of logic cells. The logic cells each include a number of combinatorial logic circuits, which have direct interconnections with the programmable interconnect structure, and a plurality of sequential logic element, such as D type flip-flops that acts as registers. The combinatorial logic circuits may be directly connected to the programmable interconnect structure as well as connected to the input terminals of the sequential logic elements. Consequently, the logic cells include both combinatorial and registered connections with the programmable interconnect structure. Moreover, one of the sequential elements may selectively receive a dedicated input from the programmable interconnect structure. The output leads of the logic cell is connected to the programmable interconnect structure through a driver that includes a protection transistor. The gate of the protection transistor is coupled to a primary charge pump that is shared with multiple drivers as well as a secondary charge pump associated with the driver.

US Patent:

6552410, Apr 22, 2003

Filed:

Aug 29, 2000

Appl. No.:

09/650773

Inventors:

David D. Eaton - San Jose CA
Kevin K. Yee - San Jose CA
E. Thomas Hart - Los Altos Hills CA
Andrew K. Chan - Palo Alto CA
Neal A. Palmer - La Jolla CA
Michael W. Dini - La Jolla CA
James Apland - Gilroy CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H01L 2200

US Classification:

257530, 257295, 257296, 257297, 257298, 257299, 257529

Abstract:

A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors. The input/output terminals around the periphery and in the interface between the programmable circuit and dedicated device are tested using JTAG registers.

US Patent:

7868441, Jan 11, 2011

Filed:

May 3, 2007

Appl. No.:

11/800175

Inventors:

David D. Eaton - San Jose CA, US
David R. Staab - Los Gatos CA, US
Ruben C. Zeta - Milpitas CA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 21/44
H01L 21/56
H01L 23/488

US Classification:

257686, 257738, 257E23023, 257E21476, 257E21502, 438108, 438613

Abstract:

A package-on-package (POP) secure module includes a BGA mesh cap, a first BGA package, and a second BGA package. The first BGA package includes a first integrated circuit (for example, a microcontroller that includes tamper detect logic). The second BGA package includes a second integrated circuit (for example, a memory). The second BGA package is piggy-back mounted to the first BGA package and the BGA mesh cap is piggy-back mounted to the second BGA package. A printed circuit board substrate member of the BGA mesh cap includes an embedded anti-tamper mesh. This mesh is connected in a protected manner within the module to the first integrated circuit. When the module is in use, a mesh embedded in an underlying printed circuit board is coupled to the BGA cap mesh so that both anti-tamper meshes are controlled by the tamper detect logic.

US Patent:

7898090, Mar 1, 2011

Filed:

Sep 28, 2007

Appl. No.:

11/904749

Inventors:

David D. Eaton - San Jose CA, US

Assignee:

IXYS CH GmbH

International Classification:

H01L 23/48

US Classification:

257777, 257778, 438127

Abstract:

A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

US Patent:

8198142, Jun 12, 2012

Filed:

Feb 18, 2011

Appl. No.:

12/932141

Inventors:

David D. Eaton - San Jose CA, US

Assignee:

IXYS CH GmbH

International Classification:

H01L 21/82

US Classification:

438127, 257778, 713178

Abstract:

A general purpose BGA security cap includes a substrate, an integrated circuit die, and an array of bond balls. The substrate includes an anti-tamper security mesh of conductors. The bond balls include outer bond balls and inner bond balls that are fixed to the underside of the substrate. The integrated circuit drives and monitors the anti-tamper security mesh and communicates data using a serial physical interface through a subset of the inner bond balls. In one example, a user has circuitry to be protected. The user purchases the BGA security cap and fits it over the circuitry to be protected such that the integrated circuit of the security cap communicates tamper detect condition information via the serial interface to the underlying protected circuitry and causes sensitive information to be erased or a program to be halted in the event of a tamper condition.

US Patent:

20110080107, Apr 7, 2011

Filed:

Oct 3, 2009

Appl. No.:

12/587169

Inventors:

Kamlapati Khalsa - San Jose CA, US
Yefim Gluzman - San Francisco CA, US
Quyen Tran - Morgan Hill CA, US
David D. Eaton - San Jose CA, US

International Classification:

H05B 37/02

US Classification:

315250, 315294

Abstract:

A multi-lamp fluorescent light fixture includes a plurality of replaceable fluorescent lamp starter units. Each starter unit has a built-in microcontroller, an RF (Radio-Frequency) receiver, and communicates wirelessly with a master unit. The plurality of starter units can be wirelessly controlled to dim the multi-lamp fixture. Each starter unit receives a DIM command. Each starter unit identified as a dimmer starter unit responds to the DIM command by turning off coupled fluorescent lamps. Starter units not identified as dimmer starter units respond by leaving coupled lamps turned on, or alternatively, turning off and quickly restarting coupled lamps. Systems of existing light fixtures are retrofitted with such wireless starter units, and thereby made controllable by a master unit so that the master unit can dim the lights if room occupancy is not detected or if sufficient ambient light is available.

US Patent:

20130211937, Aug 15, 2013

Filed:

Feb 8, 2013

Appl. No.:

13/763476

Inventors:

Marc Elbirt - Plesanton CA, US
David Eaton - San Jose CA, US

International Classification:

G06Q 20/20

US Classification:

705 17, 705 21

Abstract:

A payment provider card can be used on any credit card or bank network in order to access the user's payment provider account at the POS of non-payment provider integrated merchants. The consumer may swipe or have the card read through NFC or other means, at the POS, where the information contained in the card is communicated to the payment provider through a credit card or bank card network or rails that is already part of the merchant payment network.

US Patent:

61278459, Oct 3, 2000

Filed:

Jul 8, 1998

Appl. No.:

9/112700

Inventors:

Paige A. Kolze - Mountain View CA
Andre Stolmeijer - Washougal WA
David D. Eaton - San Jose CA

Assignee:

QuickLogic Corporation - Sunnyvale CA

International Classification:

H01L 2500
G06F 738

US Classification:

326 41

Abstract:

In a programmable device employing antifuses, first digital logic transistors the gates of which will experience a programming voltage Vpp have a greater gate insulator thickness than do second digital logic transistors the gates of which will not experience the programming voltage. The first digital logic transistors may be logic module input device transistors. The first digital logic transistors may be transistors coupled to an enable input lead where the enable input lead is couplable to a tie-high conductor or to a tie-low conductor depending on which of two antifuses is programmed.