David Asa Ewing

US Patent:

7657855, Feb 2, 2010

Filed:

May 25, 2007

Appl. No.:

11/805954

Inventors:

Nicholas A. Mezei - Thornton CO, US
David A. Ewing - Superior CO, US
Sankaranarayanan Srinivasan - San Jose CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 6, 716 5

Abstract:

Various approaches for incrementally updating the timing of an implementation of an electronic circuit design are disclosed. In one approach, a subset timing graph is selected from a primary timing graph. Alternative subset timing graphs are generated that are functionally equivalent and structurally different with respect to the selected subset timing graph. For each of the alternative timing graphs, a respective timing metric is determined. The determined timing metrics and a timing metric for the selected subset timing graph are compared. An alternative timing graph is selected in response to the comparison. Structurally different portions of the selected one of the one or more alternative timing graphs are verified with regard to the design constraints. The structurally different portions are stored to the primary timing graph.