David Steven Ford

US Patent:

20130073853, Mar 21, 2013

Filed:

Sep 20, 2012

Appl. No.:

13/623556

Inventors:

David K. Ford - Carmel CA, US

Assignee:

SunStone Information Defense Inc. - Carmel CA

International Classification:

H04L 9/32

US Classification:

713168

Abstract:

A system, methods, and apparatus for validating communications in an open architecture system are disclosed. In an example embodiment, a method includes selecting transactional information to transmit from a server to a communicatively coupled client device based on a request from the client device, selecting presentation information corresponding to the transactional information to transmit from the server to the client device, transmitting at least one message including the presentation and transactional information from the server to the client device, determining a prediction as to how the client device will render the transactional information based on the presentation information, receiving a response message from the client, and responsive to information in the response message not matching the prediction, providing an indication there is a malicious application affecting communications between the server and the client device.

US Patent:

20130305368, Nov 14, 2013

Filed:

May 9, 2013

Appl. No.:

13/890865

Inventors:

David K. Ford - Carmel CA, US

Assignee:

SunStone Information Defense Inc. - Carmel CA

International Classification:

G06F 21/56

US Classification:

726 23

Abstract:

A system, method, and apparatus for identifying and removing malicious applications are disclosed. An example apparatus includes an analysis server configured to receive from an executable application operating on a client device a data structure including information identifying processes operating on the client device during a time period and analyze the data structure to identify a malicious application by determining which of the processes on the client device were triggered after an application server was accessed by the executable application and identifying processes associated with the malicious application by comparing the determined processes to records of processes of a device similarly configured as the client device. The apparatus also includes a remover configured to determine files on the client device that are associated with the identified malicious application and transmit instructions to the executable application causing the executable application to remove the malicious application from operation on the client device.

US Patent:

58188908, Oct 6, 1998

Filed:

Sep 24, 1996

Appl. No.:

8/719423

Inventors:

David K. Ford - Gilbert AZ
Philip A. Jeffery - Tempe AZ
Phuc C. Pham - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03D 324

US Classification:

375371

Abstract:

A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

US Patent:

54184967, May 23, 1995

Filed:

Feb 7, 1994

Appl. No.:

8/192521

Inventors:

David Ford - Gilbert AZ
Emil N. Hahn - Gilbert AZ
Michael D. Reed - Mesa AZ
Nandini Srinivasan - Chandler AZ
Philip A. Jeffrey - Tempe AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03L 7099
H04L 708

US Classification:

331 2

Abstract:

A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

US Patent:

57868158, Jul 28, 1998

Filed:

May 31, 1996

Appl. No.:

8/656587

Inventors:

David M. Ford - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 300

US Classification:

345333

Abstract:

A method facilitating modification of an application's graphical user interface (GUI), particularly by application end-users. In particular, the method permits modification of the application GUI, without having to specify widgets required for the modified GUI, and without having to modify or add callback routines. Thus, users can tailor the application GUI to suit their needs without having experience in GUI development (and, in particular, with the cumbersome and error-prone tasks of widget-specification and callback programming). Elimination of the need to modify/expand the set of callback routines permits end-users to realize application GUI changes without having to form a new application executable. Thus, user-driven application GUI changes can be achieved without user access to the application source code and without the application developer's involvement.

US Patent:

61817570, Jan 30, 2001

Filed:

Apr 27, 1998

Appl. No.:

9/067757

Inventors:

Roland Neumann - Holzkirchen, DE
Phil Jeffery - Tempe AZ
David Ford - Gilbert AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03D 324

US Classification:

375375

Abstract:

Retiming means for retiming an incoming data stream 2 comprising clock generation means 22 for producing a plurality of clock signals 23 having the same frequency but differing phase, and signal processing means 24 for receiving both the plurality of clock signals 23 and the incoming data stream 2 and outputting a selected one of the clock signals 23 and a retimed data stream retimed in accordance with the selected clock signal. The signal processing means 24 includes comparison means for comparing the phase of the incoming data stream with the phase of the plurality of clock signals and selecting which clock signal to use on the basis of this comparison.

US Patent:

55635946, Oct 8, 1996

Filed:

Aug 31, 1994

Appl. No.:

8/298715

Inventors:

David K. Ford - Gilbert AZ
Bernard E. Weir - Chandler AZ

Assignee:

Motorola - Schaumburg IL

International Classification:

H03M 900

US Classification:

341100

Abstract:

A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written. Once the proper delay is determined by experimentation, the phase delay logic controls the phase of the transfer data control signal to request more data at the correct time, or present more data at the correct time, to allow maximum operating speed for the data converter.

US Patent:

63186764, Nov 20, 2001

Filed:

Jan 10, 2000

Appl. No.:

9/480066

Inventors:

Andrew E. Turner - Mountain View CA
David F. Ford - Watsonville CA
Jeffrey D. Stoen - Palo Alto CA

Assignee:

Space Systems/Loral, Inc. - Palo Alto CA

International Classification:

B64G 128

US Classification:

244165

Abstract:

A control method and improved equatorial-normal body-stabilized spacecraft that operates in an inclined orbit. The control method controls pointing of payloads (communication antennas and instruments) and solar arrays disposed on the spacecraft. The method controls the spacecraft to provide Earth-pointing payloads and sun-pointing solar arrays so that the spacecraft body and solar arrays each rotate only around a single axis, a pitch axis of the spacecraft.