David W Frame

US Patent:

6507496, Jan 14, 2003

Filed:

May 31, 2001

Appl. No.:

09/872122

Inventors:

Paul S. Levy - Chandler AZ
David Frame - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 706

US Classification:

361760, 361764, 361773, 361715, 257427, 257531, 336200

Abstract:

A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.

US Patent:

6624718, Sep 23, 2003

Filed:

Dec 14, 2000

Appl. No.:

09/736804

Inventors:

Karl H. Mauritz - Chandler AZ
David W. Frame - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01P 308

US Classification:

333 34, 333246, 333263

Abstract:

A signal transmission unit includes a first transmission line, a second transmission line, and a tapered transmission line coupling the first transmission line to the second transmission line. The tapered transmission line has a width and a length and the width changes along the length according to one or more functions. The one or more functions include but are not limited to linear functions, non-linear functions, hyperbolic functions, and exponential functions.

US Patent:

6944708, Sep 13, 2005

Filed:

Mar 22, 2002

Appl. No.:

10/104544

Inventors:

David W. Frame - Phoenix AZ, US
Edward Butler - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711106, 365222

Abstract:

A method of self-refresh in a memory array includes initializing a programmable refresh counter of a memory module to an offset value from at least another memory module in the memory array. A data line carrying a system-wide self-refresh indicator signal is interrogated to determine whether any memory module is in a self-refresh mode. The self-refresh mode for the memory module is entered if the programmable refresh counter indicates that a self-refresh cycle is due, and it is determined that no other memory modules are in the self-refresh mode.

US Patent:

7010629, Mar 7, 2006

Filed:

Dec 22, 1999

Appl. No.:

09/470542

Inventors:

David W. Frame - Aloha OR, US
Christopher J. Banyai - Chandler AZ, US
Karl H. Mauritz - Chandler AZ, US
Albert R. Nelson - Olympia WA, US
Hany M. Fahmy - University Pl. WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710100, 326 30

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.

US Patent:

20040264256, Dec 30, 2004

Filed:

Jun 26, 2003

Appl. No.:

10/609216

Inventors:

Karl Mauritz - Chandler AZ, US
David Frame - Phoenix AZ, US

International Classification:

G06F012/00

US Classification:

365/189010, 365/052000, 711/100000, 714/733000

Abstract:

According to one embodiment of the present invention, a circuit is disclosed. The circuit includes: a plurality of memory modules; a memory controller coupled to the plurality of memory modules; a plurality of bus splitters coupled between the plurality of memory modules and the memory controller to split signals communicated between the plurality of memory modules and the memory controller; and a plurality of terminators to reduce signal reflections corresponding to the split signals.