David T Golden

US Patent:

6640272, Oct 28, 2003

Filed:

Aug 31, 2000

Appl. No.:

09/652494

Inventors:

David Hartwell - Bolton MA
David Golden - Woonsocket RI
Glenn Herdeg - Acton MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710104, 710300, 710301, 710302, 710303, 710304

Abstract:

An automated backplane cable connection system (and method) for manually connecting a cluster of processor modules to other modules or I/O boxes uses a programmed server management control console which identifies connection terminals provided on the processors/I/O boxes and controls LEDs which are associated with the connection terminals, on a one to one basis. The programmed server management console uses diagnostic circuitry and causes LEDs corresponding to connection terminals engaged by a newly made cable connection to initially light up, and enables them to turn off if the newly made cable connection is proper as verified by the diagnostic circuitry. The cluster of processor modules may be connected to a plurality of I/O boxes through an Ethernet LAN. The processor modules or I/O boxes may have sufficient nonvolatile memory to remember backplane cable connections which have already been made according to user needs, as initially guided by the programmed server management control console. From the memory, replacement of cables when necessary, is facilitated, without the need for assistance by the server management console.

US Patent:

6681282, Jan 20, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/653180

Inventors:

David Golden - Woonsocket RI
Darrel Donaldson - Lancaster MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710302, 370908

Abstract:

A control system using microprocessors for communicating through a LAN to control operation of processors and input and output subsystems (IO system) of a multi-processor computer system. Each processor includes memory, and an IO system comprising a plurality of busses. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or an IO system associated with the destination processor, etc. The processors and IO system are mounted in a rack, and an IO system is associated with each processor. A rack may be hot swapped. In hot swapping, the microprocessor control system computes new routing tables for messages through the new cabling arrangement. Microprocessors, IO devices, and processor boards may be hot swapped.

US Patent:

6711693, Mar 23, 2004

Filed:

Aug 31, 2000

Appl. No.:

09/655171

Inventors:

David Golden - Woonsocket RI
Darrel Donaldson - Lancaster MA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 112

US Classification:

713400, 713600, 709400

Abstract:

The processors of a multiprocessor system are managed, or controlled, by a microprocessors referred to as MBM microprocessors, and the input/output units of the multiprocessor system are managed or controlled by microprocessors contained in PBM units. The MBM units and PBM units communicate with each other through a private local area network. The processors may be arranged into partitions by software, where the processors of a partition may exchange messages with each other, but not with other processors of the multiprocessor system. A virtual time of year clock synchronizes the microprocessors of the MBM and PBM units within a partition to form a âbase timeâ. In the event that the operating system of a partition changes the time within that partition, a âdelta timeâ is computed such that the base time plus the delta time gives the set time. The delta time is stored in a database which is replicated within all MBM and PBM microprocessors. A processor determines its current time by reading a register in which current time is written as partition base time plus partition delta time.

US Patent:

6920516, Jul 19, 2005

Filed:

Aug 31, 2001

Appl. No.:

09/944516

Inventors:

David W. Hartwell - Bolton MA, US
Samuel H. Duncan - Arlington MA, US
David T. Mayo - Boxboro MA, US
David J. Golden - Woonsocket RI, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F013/24

US Classification:

710263, 710262, 710266

Abstract:

An anti-starvation interrupt protocol for use in avoiding livelock in a multiprocessor computer system is provided. At least one processor is configured to include first and second control status registers (CSRs). The first CSR buffers information, such as interrupts, received by the processor, while the second CSR keeps track of the priority level of the interrupts. When an interrupt controller receives an interrupt, it issues a write transaction to the first CSR at the processor. If the first CSR has room to accept the write transaction, the processor returns an acknowledgement, whereas if the first CSR is already full, the processor returns a no acknowledgment. In response to a no acknowledgment, the interrupt controller increments an interrupt starvation counter, and checks to see whether the counter exceeds a threshold. If not, the interrupt controller waits a preset time and reposts the write transaction. If it does, the interrupt controller issues a write transaction having a higher priority to the second CSR.

US Patent:

6973517, Dec 6, 2005

Filed:

Aug 31, 2000

Appl. No.:

09/652458

Inventors:

David Golden - Woonsocket RI, US
Dennis Mazur - Worcester MA, US
Richard Edward Bracken - Boston MA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F013/00

US Classification:

710104, 710302

Abstract:

The invention is a control system using microprocessors which communicate through a Local Area Network (private LAN) to control operation of both processors and input and output subsystems (IO system) of a multiprocessor computer system. The processors each have memory associated therewith, and each processor has an IO system comprising a plurality of busses such as PCI busses, associated therewith. The processors are cabled together in a mesh arrangement so that messages can be transferred between any of the processors and delivered to memory associated with the destination processor, or delivered to an IO system associated with the destination processor, etc. The microprocessors are powered on when power is applied to the chassis of the multiprocessor system, and the microprocessors then control the processors of the multiprocessor system, including applying power to the processors, forming hard partitions containing selected processors, computing routes from a processor to a memory associated with any processor for read and write transactions, computing routes to IO subsystems associated with any processor of the hard partition, forming partition boundaries so that processors in one hard partition cannot read and write to memory or IO systems associated with processors in another hard partition, forming soft partitions of processors, controlling boot-up of operating systems executing on the processors of the multiprocessor computer system, removing power from a failed processor, providing power to a repaired processor, etc.