David Eugene Grider

US Patent:

6830945, Dec 14, 2004

Filed:

Mar 12, 2003

Appl. No.:

10/386960

Inventors:

Jeong Sun Moon - Chatsworth CA
Paul Hashimoto - Los Angeles CA
Wah S. Wong - Montebello CA
David E. Grider - Charlotte NC

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 2100

US Classification:

438 22, 438 94

Abstract:

A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

US Patent:

7033961, Apr 25, 2006

Filed:

Jul 15, 2003

Appl. No.:

10/620205

Inventors:

Joseph Smart - Morrisville NC, US
Brook Hosse - Huntersville NC, US
Shawn Gibb - Charlotte NC, US
David Grider - Huntersville NC, US
Jeffrey B. Shealy - Huntersville NC, US

Assignee:

RF Micro Devices, Inc. - Greensboro NC

International Classification:

H01L 21/26

US Classification:

438796, 438 46, 438795

Abstract:

The present invention relates to an epitaxial structure having one or more structural epitaxial layers, including a gallium nitride (GaN) layer, which is deposited on a substrate, and a method of growing the epitaxial structure, wherein the structural epitaxial layers can be separated from the substrate. In general, a sacrificial epitaxial layer is deposited on the substrate between the substrate and the structural epitaxial layers, and the structural epitaxial layers are deposited on the sacrificial layer. After growth, the structural epitaxial layers are separated from the substrate by oxidizing the sacrificial layer. The structural epitaxial layers include a nucleation layer deposited on the sacrificial layer and a gallium nitride layer deposited on the nucleation layer. Optionally, the oxidation of the sacrificial layer may also oxidize the nucleation layer.

US Patent:

7247893, Jul 24, 2007

Filed:

Sep 1, 2004

Appl. No.:

10/932811

Inventors:

Jeong Sun Moon - Chatsworth CA, US
Paul Hashimoto - Los Angeles CA, US
Wah S. Wong - Montebello CA, US
David E. Grider - Charlotte NC, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29/20

US Classification:

257200, 257194, 257201, 257E29249, 438167, 438172

Abstract:

A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

US Patent:

7514759, Apr 7, 2009

Filed:

Apr 11, 2005

Appl. No.:

11/104395

Inventors:

Sarabjit Mehta - Calabasas CA, US
David E. Grider - Charlotte NC, US
Wah S. Wong - Montebello CA, US

Assignee:

HRL Laboratories, LLC - Malibu CA

International Classification:

H01L 29/84
H01L 21/00

US Classification:

257416, 438 55

Abstract:

A process for fabricating a combined micro electromechanical/gallium nitride structure. The micro electromechanical structure comprises a piezoelectric device, such as a piezoelectric switch or a bulk acoustic wave device. According to the process, high Q compact bulk acoustic wave resonators can be built. The process is applicable to technologies such as tunable planar filter technology, amplifier technology and high speed analog-to-digital converters.

US Patent:

20140374773, Dec 25, 2014

Filed:

Jun 25, 2013

Appl. No.:

13/926313

Inventors:

- Durham NC, US
Craig Capell - Hillsborough NC, US
Charlotte Jonas - Morrisville NC, US
David Grider - Wake Forest NC, US

International Classification:

H01L 27/092
H01L 29/16
H01L 27/098

US Classification:

257 77

Abstract:

A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.