David J Grider

US Patent:

20140374773, Dec 25, 2014

Filed:

Jun 25, 2013

Appl. No.:

13/926313

Inventors:

- Durham NC, US
Craig Capell - Hillsborough NC, US
Charlotte Jonas - Morrisville NC, US
David Grider - Wake Forest NC, US

International Classification:

H01L 27/092
H01L 29/16
H01L 27/098

US Classification:

257 77

Abstract:

A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.