David Scott Hanson

US Patent:

6847527, Jan 25, 2005

Filed:

Jul 19, 2002

Appl. No.:

10/199926

Inventors:

Mark F. Sylvester - Fall Creek WI, US
David A. Hanson - Eau Claire WI, US
William G. Petefish - Chippewa Falls WI, US

Assignee:

3M Innovative Properties Company - St. Paul MN

International Classification:

H05K 706
H05K 103
H05K 342
H05K 346

US Classification:

361763, 361762, 361793, 361795, 174255, 174257, 174258, 174260, 174262, 257691, 29832, 29846, 29852

Abstract:

An interconnect module for an integrated circuit chip incorporates a thin, high dielectric constant embedded capacitor structure to provide reduced power distribution impedance, and thereby promote higher frequency operation. The interconnect module is capable of reliably attaching an integrated circuit chip to a printed wiring board via solder ball connections, while providing reduced power distribution impedance of less than or equal to approximately 0. 60 ohms at operating frequencies in excess of 1. 0 gigahertz.

US Patent:

58634460, Jan 26, 1999

Filed:

Nov 8, 1996

Appl. No.:

8/752493

Inventors:

David A. Hanson - Altoona WI

Assignee:

W. L. Gore & Associates, Inc. - Newark DE

International Classification:

B44C 122

US Classification:

216 16

Abstract:

A method for determining a fiducial misregistration of conductive layers of a laminated substrate by providing a plurality of alternatingly disposed dielectric layers and conductive layers. A predetermined area of resistive material is formed as part of at least one conductive layer. Each predetermined area of resistive material is formed at a same corresponding location in each respective conductive layer, and each predetermined area of resistive material has a first end and a second end. A through-via is formed and connected to each predetermined area of resistive material between the first and second ends of each respective predetermined area. A total resistance is determined between the first end and the second end of each predetermined area of resistive material. A first fractional resistance is determined between the first end of each predetermined area of resistive material and the through-via. A second fractional resistance is determined between the second end of each predetermined area of resistive material and the through-via.

US Patent:

58797866, Mar 9, 1999

Filed:

Nov 8, 1996

Appl. No.:

8/745592

Inventors:

John J. Budnaitis - Eau Claire WI
Paul J. Fischer - Eau Claire WI
David A. Hanson - Altoona WI
David B. Noddin - Eau Claire WI
Mark F. Sylvester - Eau Claire WI
William George Petefish - Eau Claire WI

Assignee:

W. L. Gore & Associates, Inc. - Newark DE

International Classification:

B32B 900
H01L 23053

US Classification:

428209

Abstract:

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

US Patent:

6021564, Feb 8, 2000

Filed:

Sep 23, 1998

Appl. No.:

9/159140

Inventors:

David A. Hanson - Altoona WI

Assignee:

W. L. Gore & Associates, Inc. - Newark DE

International Classification:

H01K 310

US Classification:

29852

Abstract:

A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

US Patent:

58410759, Nov 24, 1998

Filed:

Jan 28, 1998

Appl. No.:

/014885

Inventors:

David A. Hanson - Altoona WI

Assignee:

W. L. Gore & Associates, Inc. - Newark DE

International Classification:

H05K 100

US Classification:

174250

Abstract:

A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

US Patent:

60116978, Jan 4, 2000

Filed:

Nov 18, 1998

Appl. No.:

9/195054

Inventors:

John J. Budnaitis - Eau Claire WI
Paul J. Fischer - Eau Claire WI
David A. Hanson - Altoona WI
David B. Noddin - Eau Claire WI
Mark F. Sylvester - Eau Claire WI
William George Petefish - Eau Claire WI

Assignee:

W. L. Gore & Associates, Inc. - Newark DE

International Classification:

H05K 702
H05K 103
H05K 109
H05K 116

US Classification:

361792

Abstract:

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

US Patent:

53553977, Oct 11, 1994

Filed:

Sep 24, 1992

Appl. No.:

7/950628

Inventors:

David A. Hanson - Altoona WI
Edward C. Priest - Eau Claire WI

Assignee:

Cray Research, Inc. - Chippewa Falls WI

International Classification:

H03K 17296
H03K 1728
H03K 1722

US Classification:

377 56

Abstract:

Utilization circuits, such as logic chip circuits, are prevented from receiving the initial one or more pulses of a train of clock pulses produced after the master system clock is started, while the pulses of that train occurring thereafter are coupled to the utilization circuit. This prevents the skew usually present between the initial pulses of the train relative to the subsequent train pulses from adversely effecting operation of the utilization circuits. This clock swallowing preferably blocks a certain predetermined number of initial clock pulses from reaching the rest of the circuitry, although the system is adaptable to allow preselection of the number of such swallowed pulses.

US Patent:

61845892, Feb 6, 2001

Filed:

Nov 18, 1998

Appl. No.:

9/195052

Inventors:

John J. Budnaitis - Eau Claire WI
Paul J. Fischer - Eau Claire WI
David A. Hanson - Altoona WI
David B. Noddin - Eau Claire WI
Mark F. Sylvester - Eau Claire WI
William George Petefish - Eau Claire WI

International Classification:

H01L 2302

US Classification:

257924

Abstract:

A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.