David L Hanson

US Patent:

6359471, Mar 19, 2002

Filed:

Jan 27, 2000

Appl. No.:

09/491645

Inventors:

Gerhard Mueller - Wappingers Falls NY
David R. Hanson - Brewster NY

Assignee:

Infineon Technologies North America Corp. - Cupertino CA
International Business Machines Corporation - Armonk NY

International Classification:

H03K 190175

US Classification:

326 81, 326 86, 326 30, 326 68, 326 57, 326 56

Abstract:

A mixed swing voltage repeater circuit operates with reduced voltage signals, that is signals having a voltage level that is below a full swing voltage level. The mixed swing voltage repeater circuit is configured to be coupled to the signal line and has an input node coupled to a first portion of the signal line for receiving a reduced voltage signal and an output node coupled to a second portion of the signal line for outputting a full swing voltage signal. In another embodiment, the mixed swing voltage repeater circuit is configured to be coupled to the signal line and has an input node coupled to a first portion of the signal line for receiving a full swing voltage signal and an output node coupled to a second portion of the signal line for outputting a reduced swing voltage signal.

US Patent:

6370055, Apr 9, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/795761

Inventors:

David Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY
Toshiaki Kirihata - Poughkeepsie NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

G11C 506

US Classification:

365 63, 365 69, 36523003, 365214, 365 51

Abstract:

There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.

US Patent:

6426658, Jul 30, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/676864

Inventors:

Gerhard Mueller - Meitingen, DE
David Russell Hanson - Brewster NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03K 190185

US Classification:

327112, 327208, 327214, 327333, 326 81, 326 83

Abstract:

A buffer circuit that operates with reduced voltage input and output signals receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is from 0 volts to V , where V is less than V , the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.

US Patent:

6522171, Feb 18, 2003

Filed:

Jan 11, 2001

Appl. No.:

09/759011

Inventors:

David R. Hanson - Brewster NY
Toshiaki Kirihata - Poughkeepsie NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 95, 326 98

Abstract:

A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

US Patent:

6529054, Mar 4, 2003

Filed:

Oct 22, 1999

Appl. No.:

09/425329

Inventors:

David Russell Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Infineon Technologies AG - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03L 716

US Classification:

327144, 327154, 327288, 327294, 327394, 375354, 375377

Abstract:

A synchronized data capture circuit configured to synchronize capturing of data in a first plurality of data signals with a first plurality of timing signals to output a synchronized data capture signal. The synchronized data capture circuit includes a timer generator having a first timer generator output. The timer generator is coupled to receive the first plurality of timing signals and to serially output on the first timer generator output, as a first high frequency timing pulse stream, first timing pulses responsive to timing pulses of the plurality of timing signals. The first high frequency timing pulse stream has a timing pulse stream frequency that is higher than a timing input frequency associated with one of the first plurality of timing signals. The synchronized data capture circuit also includes first plurality of data driver circuits coupled to receive the first plurality of data signals and the plurality of timing signals. The first plurality of data driver circuits are configured to serially output, as a first high frequency data stream, first data pulses responsive to the timing pulses of the plurality of timing signals and data pulses of the first plurality of data signal.

US Patent:

6574127, Jun 3, 2003

Filed:

Mar 29, 2001

Appl. No.:

09/820592

Inventors:

Louis L. Hsu - Fishkill NY
Rajiv V. Joshi - Yorktown Heights NY
David R. Hanson - Brewster NY

Assignee:

IBM Corporation - Armonk NY

International Classification:

G11C 506

US Classification:

365 63, 365206

Abstract:

A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differential signal includes at least one vertical twist in which the true and complementary signal components of the differential signal change position from the one metal level of the plurality of metal levels to another level.

US Patent:

6668031, Dec 23, 2003

Filed:

Aug 19, 1999

Appl. No.:

09/377588

Inventors:

David Russell Hanson - Brewster NY
Gerhard Mueller - Wappingers Falls NY

Assignee:

Infineon Technologies AG
International Business Machines Corporation - Armonk NY

International Classification:

H04L 700

US Classification:

375355, 327141

Abstract:

A synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal.

US Patent:

6683486, Jan 27, 2004

Filed:

Apr 2, 2002

Appl. No.:

10/114221

Inventors:

David Hanson - Brewster NY
Gerhard Mueller - Meitingen, DE
Toshiaki Kirihata - Poughkeepsie NY

Assignee:

Infineon Technologies Ag - Munich
International Business Machines Corporation - Armonk NY

International Classification:

H03L 500

US Classification:

327333

Abstract:

A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.