David George Harper

US Patent:

6801207, Oct 5, 2004

Filed:

Oct 9, 1998

Appl. No.:

09/169314

Inventors:

Brett A. Tischler - Longmont CO
Carl D. Dietz - Blue Ridge TX
David F. Bremner - Boulder CO
David T. Harper - Seattle WA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G09G 536

US Classification:

345557, 345503, 345531, 345537, 711122, 711128, 711537

Abstract:

A highly integrated multimedia processor employs a shared cache between tightly coupled central processing and graphics units to provide the graphics unit access to data retrieved from system memory or data processed by the central processing unit before the data is written-back or written-through to system memory, thus reducing system memory bandwidth requirements. Regions in the shared cache can also be selectively locked down thereby disabling eviction or invalidation of a selected region, to provide the graphics unit with a local scratchpad area for applications such as, but not limited to, temporary video line buffering storage for filter applications and composite buffering for blending texture maps in multi-pass rendering.

US Patent:

8412889, Apr 2, 2013

Filed:

Oct 16, 2008

Appl. No.:

12/252467

Inventors:

David Harper - Seattle WA, US
Burton Smith - Seattle WA, US

Assignee:

Microsoft Corporation - Redmond WA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711145, 711E12026

Abstract:

A low-overhead conditional synchronization instruction operates on a synchronization variable which includes a lock bit, a state specification, and bits for user-defined data. The instruction specifies the memory address of the synchronization variable and a condition. During the synchronization instruction the condition is compared to the state specification within an atomic region. The match succeeds if the condition matches the state specification and the lock bit is clear. The synchronization instruction may operate with a cache under a cache coherency protocol, or without a cache, and may include a timeout operand.

US Patent:

20070198785, Aug 23, 2007

Filed:

Feb 15, 2007

Appl. No.:

11/675549

Inventors:

Peter M. Kogge - Granger IN, US
Jay B. Brockman - Granger IN, US
David Tennyson Harper - Seattle WA, US
Burton Smith - Seattle WA, US
Charles David Callahan - Seattle WA, US

International Classification:

G06F 15/00

US Classification:

711154, 712 14

Abstract:

Embodiments of the present invention provide a class of computer architectures generally referred to as lightweight multi-threaded architectures (LIMA). Other embodiments may be described and claimed.

US Patent:

20130087850, Apr 11, 2013

Filed:

Oct 11, 2011

Appl. No.:

13/270780

Inventors:

Scott J. Alberhasky - Portland OR, US
David Harper - Battle Ground WA, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H01L 27/088
H01L 21/336

US Classification:

257329, 438268, 257E2706, 257E2141

Abstract:

Semiconductor devices that include a trench with conductive material for connecting a VDMOS device to a LDMOS device are described. The semiconductor devices include a substrate having a first region and a second region, wherein the second region is disposed on the first region. A trench extends from a top surface of the second region to the first region. The semiconductor substrate includes a VDMOS device formed proximate to the top surface of the second region and a LDMOS device that is also formed proximate to the top surface of the second region. The drain region of the VDMOS device is electrically connected to the source region of the LDMOS device by way of a conductive material disposed in the trench.

US Patent:

60147474, Jan 11, 2000

Filed:

Sep 30, 1997

Appl. No.:

8/941520

Inventors:

Aleph Fackenthall - Portland OR
David Harper - Lacey WA
Joseph Bursey - Hillsboro OR
Brad Bickford - Beaverton OR
Brian G. Stern - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300
G06F 300
G06F 116
G08B 1314

US Classification:

713200

Abstract:

A tamper detect device is provided to a chassis of a system. The tamper detect device provides a signal when the chassis is opened while at least a part of the system is under power. In one embodiment, the signal is used to produce an immediate warning. In another embodiment, the tamper detect device is incorporated into the system and the warning is audio. In another embodiment, the warning is continually provided until the chassis cover is closed, the system is unplugged, or the tamper detect device is bypassed. In another embodiment, the system is a computer system.

US Patent:

20200089503, Mar 19, 2020

Filed:

Dec 18, 2018

Appl. No.:

16/224600

Inventors:

- Redmond WA, US
David T. Harper - Seattle WA, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

G06F 9/38
G06F 9/30

Abstract:

Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.

US Patent:

20190236009, Aug 1, 2019

Filed:

Feb 2, 2018

Appl. No.:

15/887640

Inventors:

- Redmond WA, US
Aaron L. Smith - Seattle WA, US
Gagan Gupta - Bellevue WA, US
David T. Harper - Seattle WA, US

Assignee:

Microsoft Technology Licensing, LLC - Redmond WA

International Classification:

G06F 12/0804
G06F 9/30
G06F 9/38

Abstract:

Systems and methods are disclosed for performing wide memory operations for a wide data cache line. In some examples of the disclosed technology, a processor having two or more execution lanes includes a data cache coupled to memory, a wide memory load circuit that concurrently loads two or more words from a cache line of the data cache, and a writeback circuit situated to send a respective word of the concurrently-loaded words to a selected execution lane of the processor, either into an operand buffer or bypassing the operand buffer. In some examples, a sharding circuit is provided that allows bitwise, byte-wise, and/or word-wise manipulation of memory operation data. In some examples, wide cache loads allows for concurrent execution of plural execution lanes of the processor.

US Patent:

20180081379, Mar 22, 2018

Filed:

Nov 28, 2017

Appl. No.:

15/825082

Inventors:

- Redmond WA, US
David T. HARPER - Seattle WA, US
Stephen HEIL - Sammamish WA, US
Eric C. PETERSON - Woodinville WA, US
Adam B. GLASS - Cambridge, GB
David Alex BUTLER - Cambridge, GB
Austin Nicholas DONNELLY - Cambridge, GB
Antony Ian Taylor ROWSTRON - Cambridge, GB
Sergey LEGTCHENKO - Cambridge, GB

International Classification:

G05D 23/19
G06F 1/26
G06F 1/20
G06F 3/06
G06F 13/40

Abstract:

Low cost storage for write once read rarely data is described. In an embodiment a storage device comprises a plurality of hard disk drives connected to a server via an interconnect fabric. The storage device comprises a cooling system which is only capable of cooling a first subset of the hard disk drives and a power supply system which is only capable of powering a second subset of the hard disk drives and in some examples, the interconnect fabric may be only capable of providing full bandwidth for a third subset of the hard disk drives. Each subset may comprise only a small fraction of hard disk drives. A control mechanism, which may be implemented in software, is provided which controls which hard disk drives are active at any time in order that the constraints set by the cooling and power supply systems and interconnect fabric are not violated.