David J Hart

US Patent:

7768364, Aug 3, 2010

Filed:

Jun 9, 2008

Appl. No.:

12/135431

Inventors:

David Hart - Cornelius OR, US
Sudarsan Uppili - Portland OR, US
Guillaume Bouche - Beaverton OR, US

Assignee:

Maxim Integrated Products, Inc. - Sunnyvale CA

International Classification:

H03H 9/215
H01L 41/047

US Classification:

333187, 310364

Abstract:

Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W.

US Patent:

7966722, Jun 28, 2011

Filed:

Jul 11, 2008

Appl. No.:

12/172079

Inventors:

David Hart - Cornelius OR, US
David McDonald - Hillsboro OR, US
Guillaume Bouche - Beaverton OR, US
Sudarsan Uppili - Portland OR, US

Assignee:

TriQuint Semiconductor, Inc. - Hillsboro OR

International Classification:

H05K 3/02

US Classification:

29847, 29832, 29831, 29852, 29846, 29 2535

Abstract:

Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

US Patent:

8643067, Feb 4, 2014

Filed:

Sep 30, 2011

Appl. No.:

13/249529

Inventors:

Scott J. Alberhasky - Portland OR, US
David E. Hart - Cornelius OR, US
Sudarsan Uppili - Portland OR, US

Assignee:

Maxim Integrated Products, Inc. - San Jose CA

International Classification:

H01L 29/66

US Classification:

257263, 257302, 257328, 257E29262

Abstract:

Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.