David C Hawley

US Patent:

53369505, Aug 9, 1994

Filed:

Feb 8, 1993

Appl. No.:

8/015415

Inventors:

Sanjay Popli - Sunnyvale CA
Scott Pickett - Los Gatos CA
David Hawley - Belmont CA
Shankar Moni - Santa Clara CA
Rafael C. Camarota - San Jose CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 19177

US Classification:

307465

Abstract:

The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins. The array further includes a configuration circuit for generating external addresses and that can be controlled through a data configuration file fetched from an external storage medium.

US Patent:

53291808, Jul 12, 1994

Filed:

Feb 8, 1993

Appl. No.:

8/015347

Inventors:

Sanjay Popli - Sunnyvale CA
Scott Pickett - Los Gatos CA
David Hawley - Belmont CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 19177

US Classification:

307465

Abstract:

The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of horizontal rows of logic cells and a plurality of vertical columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array further includes a dynamic tristate bus driver associated with each logic cell and connectable to the local busses associated with the corresponding logic cell and means for controlling the dynamic tri-state driver through one or more combinations of inputs to the logic cell.

US Patent:

52988058, Mar 29, 1994

Filed:

Apr 8, 1993

Appl. No.:

8/044921

Inventors:

Tim Garverick - Cupertino CA
Jim Sutherland - Sunnyvale CA
Sanjay Popli - Sunnyvale CA
Venkata Alturi - Sunnyvale CA
Arthur Smith - San Carlos CA
Scott Pickett - Los Gatos CA
David Hawley - Belmont CA
Shao-Pin Chen - San Jose CA
Shankar Moni - Santa Clara CA
Benjamin S. Ting - Saratoga CA
Rafael C. Camarota - San Jose CA
Frederick Furtek - Menlo Park CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03K 19177

US Classification:

307465

Abstract:

A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.

US Patent:

50557122, Oct 8, 1991

Filed:

Apr 5, 1990

Appl. No.:

7/504967

Inventors:

David W. Hawley - Belmont CA
Scott K. Pickett - San Jose CA

Assignee:

National Semiconductor Corp. - Santa Clara CA

International Classification:

G06F 900

US Classification:

307465

Abstract:

A programmable logic device is constructed having a novel architecture. A plurality of control input signals are applied to a programmable mapping array in order to generate control functions for data path gating, latching, or modification. The programmable control functions provide flexibility to the designer, while the fixed data path logic is independent of the programmable array. The logic array and data path logic are fabricated on the same integrated circuit, therefore obviating the need for input/output buffers which would be necessary if the device were constructed utilizing discrete components. This enhances the performances of the device. Since the data path does not travel through the array, its performance is not affected by the programmability. If desired, the programmable array can be formed of mask programmable devices, fused programmable devices, or register based circuitry, for example, using RAM cells.