David M Heap

US Patent:

D583830, Dec 30, 2008

Filed:

Sep 19, 2006

Appl. No.:

29/266327

Inventors:

Benjamin S. Burkhart - Stillwater OK, US
David M. Heap - Stillwater OK, US
Keith W. Schmidt - Stillwater OK, US

Assignee:

Brunswick Corporation - Lake Forest IL

International Classification:

1501

US Classification:

D15 4

US Patent:

20020151039, Oct 17, 2002

Filed:

Aug 12, 1999

Appl. No.:

09/373041

Inventors:

CARL T. WITTWER - SALT LAKE CITY UT, US
MARK G. HERRMANN - CLINTON UT, US
DAVID M. HEAP - BOUNTIFUL UT, US

International Classification:

C12M001/40

US Classification:

435/286100, 435/287200, 435/303100, 435/091200, 392/323000, 204/601000

Abstract:

A system for thermal cycling a sample utilizing electrolyte conductance heating. An electric current is passed through the sample to increase its temperature due to resistance heating. As the sample acquires more thermal energy its viscosity changes, which causes a change in resistance. Because of this characteristic, temperature of the sample can be measured as a function of resistance and temperature can be controlled using resistance of the solution as feedback to a circuit which controls the heating of the sample by electrical conductance.

US Patent:

42311063, Oct 28, 1980

Filed:

Jul 13, 1978

Appl. No.:

5/924242

Inventors:

David L. Heap - Centerville UT
Allen L. Kenner - Magna UT

Assignee:

Sperry Rand Corporation - New York NY

International Classification:

G06F 900

US Classification:

364900

Abstract:

Performance monitor apparatus is adapted to monitor various computer program events such as the length of time required to execute a particular program, the number of times a particular program or instruction sequence is executed during some predetermined period, etc. The apparatus includes a buffer for receiving an instruction data word from a data processor and for temporarily storing the data word, a register having a plurality of bistable elements each of which is adapted to produce either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, a select logic circuit for applying a select signal to a particular bistable element identified by certain bits of the instruction data word stored in the buffer, and an operation logic circuit for supplying to the bistable elements either a first or second operation signal as determined by certain other bits of the instruction data word stored in the buffer. Each bistable element represents a different event or occurrence in a computer program being monitored and the signals produced by the bistable elements indicate the nature of the monitoring operation to be performed. The signals are supplied to timing and counting apparatus which then either measures the time over which the signals are produced or increments a count in response to receiving the signals.