David A Holmes

US Patent:

6459883, Oct 1, 2002

Filed:

Jul 31, 2001

Appl. No.:

09/920094

Inventors:

Ravi Subramanian - Mountain View CA
Keith Rieken - Cupertino CA
Uma Jha - Placentia CA
David M. Holmes - Cupertino CA
Joel D. Medlock - Los Gatos CA
Murali Krishnan - San Jose CA

Assignee:

Morphics Technology, Inc. - Campbell CA

International Classification:

H04B 1700

US Classification:

455 671, 455 676, 375142, 375144

Abstract:

A rake receiver in accordance with an exemplary embodiment of this invention is configurable by an external agent (e. g. , microcontroller, DSP, or state machine) to suit the particular requirements of different spread spectrum systems. In an exemplary embodiment, the receiver includes multiple fingers. Each finger includes a plurality of generic despreaders/descramblers, a plurality of generic dechannelizers coupled to the despreaders/descramblers, and at least one timing estimation controller coupled to the despreaders/descramblers. The finger also includes at least one phase estimation controller, at least one frequency estimation controller, and at least one energy estimation controller all coupled to the generic dechannelizers.

US Patent:

7039915, May 2, 2006

Filed:

Dec 30, 2003

Appl. No.:

10/750532

Inventors:

Chakki Kavoori - San Jose CA, US
Keith Reiken - Saratoga CA, US
David M. Holmes - Cupertino CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

G06F 9/46
G06F 12/00

US Classification:

718104, 707204

Abstract:

An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.

US Patent:

7065128, Jun 20, 2006

Filed:

Jul 31, 2001

Appl. No.:

09/920095

Inventors:

Joel D. Medlock - Los Gatos CA, US
Keith Rieken - Cupertino CA, US
David M. Holmes - Cupertino CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H04B 1/69

US Classification:

375147

Abstract:

An apparatus for reducing storage requirements and for allowing reuse of multiple rake fingers in a spread spectrum system includes a decimation circuit having an associated decimation factor, a memory coupled to the decimation circuit, and an interpolation circuit having an interpolation factor coupled to the memory. The decimation circuit decimates the sampling rate of received data to produce a decimated rate. The received data is stored in the memory at the decimated rate. The decimated rate is later increased by the interpolation circuit by the interpolation factor when the stored data is retrieved from the memory. The memory is a circular buffer or a single port RAM that is accessible by multiple rake fingers substantially simultaneously via selector circuits.

US Patent:

D530789, Oct 24, 2006

Filed:

May 2, 2005

Appl. No.:

29/229000

Inventors:

David G. Holmes - Santa Cruz CA, US

International Classification:

2301

US Classification:

D23249

US Patent:

7230978, Jun 12, 2007

Filed:

Dec 28, 2001

Appl. No.:

10/040727

Inventors:

Stefan Johannes Bitterlich - Aachen, DE
David Morris Holmes - Cupertino CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H04B 1/38
H04L 5/16

US Classification:

375219, 375220, 375222

Abstract:

A reconfigurable channel CODEC (encoder and decoder) processor for a wireless communication system is disclosed. A high degree of user programmability and reconfigurability is provided by the channel CODEC processor. In particular, the reconfigurable channel CODEC processor includes processor cores and algorithm-specific kernels that contain logic circuits tailored for carrying out predetermined but user-configurable decoding and encoding algorithms. The interconnects between the processor cores and the algorithm-specific kernels are also user-configurable. Thus, the same hardware can be reconfigured for many different wireless communication standards.

US Patent:

7233810, Jun 19, 2007

Filed:

Aug 3, 2001

Appl. No.:

09/922484

Inventors:

Joel D. Medlock - Los Gatos CA, US
Uma Jha - Placentia CA, US
David M. Holmes - Cupertino CA, US
Andrea Y. J. Chen - Campbell CA, US
Madasamy Kartheepan - San Jose CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H04B 1/38

US Classification:

455560, 455561, 455101

Abstract:

A dynamically reconfigurable universal transmitter system is disclosed herein. The electronic device includes multiple transmitter resources for generating transmission signals, an output bus, and an antenna summer coupled to the output bus. The output bus is selectively coupled to the plurality of transmitter resources and it selectively receives transmission signals from the plurality of transmission resources. The antenna summer stores transmission signals received on the output bus.

US Patent:

7512951, Mar 31, 2009

Filed:

Jul 31, 2001

Appl. No.:

09/920093

Inventors:

Keith Rieken - Cupertino CA, US
Joel D. Medlock - Los Gatos CA, US
David M. Holmes - Cupertino CA, US

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

G06F 9/46
G06F 15/76
G06F 13/00
G06F 3/00

US Classification:

718107, 718100, 718102, 712 1, 711100, 711129, 710 1

Abstract:

A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

US Patent:

7536691, May 19, 2009

Filed:

Aug 9, 2001

Appl. No.:

09/927906

Inventors:

Chakki Kavoori - San Jose CA, US
Keith Rieken - Cupertino CA, US
David M. Holmes - Cupertino CA, US

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

G06F 9/46
G06F 15/173

US Classification:

718104, 718101, 709226

Abstract:

An architecture and method for dynamic resource allocation and scheduling in a communication device is disclosed herein. The method of controlling hardware resources in a communication device having a processor, a computer readable memory, and at least one hardware resource coupled to each other includes several steps. The first step locates a memory address in the computer readable memory that is associated with a first hardware resource. In the next step, control information associated with the first memory address is transmitted to the first hardware resource for it to be operated. In the last step, a pointer associated with the first address that locates a subsequent address for a subsequent hardware resource, is read.