David E Hutton

US Patent:

7266580, Sep 4, 2007

Filed:

May 12, 2003

Appl. No.:

10/435976

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
David S. Hutton - Poughkeepsie NY, US
Christopher A. Krygowski - Lagrangeville NY, US
Sheryll H. Veneracion - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/52

US Classification:

708625, 708628

Abstract:

A method and apparatuses for performing binary multiplication on signed and unsigned operands of various lengths is discussed herein. It is a concept that may be split into two parts, the first of which is the multiplication hardware itself, a compact, less than-full sized multiplier employing Booth or other type of recoding methods upon the multiplier to reduce the number of partial products per scan, and implemented in such a manner so that a multiplication operation with large operands may be broken into subgroups of operations that will fit into this mid-sized multiplier whose results, here called modular products, may be knitted back together to form a correct, final product. The second part of the concept is the supporting hardware used to separate the operands into subgroups and input the data and control signals to the multiplier, and the algorithms and apparatuses used to align and combine the modular products properly to obtain the final product. These algorithms used to obtain a result as specified by the operation may be as varied as the supporting hardware with which the multiplier may be used, making this multiplier a very flexible and powerful design.

US Patent:

7475193, Jan 6, 2009

Filed:

Jan 18, 2006

Appl. No.:

11/334280

Inventors:

David S. Hutton - Poughkeepsie NY, US
Kathryn M. Jackson - Poughkeepsie NY, US
Keith N. Langston - Woodstock NY, US
Pak-kin Mak - Poughkeepsie NY, US
Bruce Wagar - Tempe AZ, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711130, 711122

Abstract:

A dual system shared cache directory structure for a cache memory performs the role of an inclusive shared system cache, i. e. , data, and system control, i. e. , coherency. The system includes two separate system cache directories in the shared system cache. The two separate cache directories are substantially equal in size and collectively large enough to contain all of the processor cache directory entries, but with only one of these separate cache directories hosting system-cache data to back the most recent fraction of data accessed by the processors. The other cache directory retains only addresses, including addresses of lines LRUed out from the first cache directory and the identity of the processor using the data. Thus by this expedient, only the directory known to be backed by system cached data will be evaluated for system cache memory data.

US Patent:

7490121, Feb 10, 2009

Filed:

May 16, 2007

Appl. No.:

11/749239

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
David S. Hutton - Poughkeepsie NY, US
Christopher A. Krygowski - LaGrangeville NY, US
Sheryll H. Veneracion - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/52

US Classification:

708625

Abstract:

A method of implementing binary multiplication in a processing device includes obtaining a multiplicand and a multiplier from a storage device; in the event the multiplier is larger than a selected length, partitioning the multiplier into a plurality of multiplier subgroups; in the event the multiplicand is larger than a selected length, partitioning the multiplicand into a plurality of multiplicand subgroups and at least one of zeroing out of unused bits of the multiplicand subgroup and sign-extending a smaller portion of the multiplicand subgroup; establishing a plurality of multiplicand multiples based on at least one of a selected multiplicand subgroup of the plurality of multiplicand subgroups and the multiplicand; selecting one or more of the multiplicand multiples of the plurality of multiplicand multiples based on the each multiplier subgroup of the plurality of multiplier subgroups; and generating a first modular product based on the selected multiplicand multiples.

US Patent:

7577795, Aug 18, 2009

Filed:

Jan 25, 2006

Appl. No.:

11/339196

Inventors:

David S. Hutton - Poughkeepsie NY, US
Kathryn M. Jackson - Poughkeepsie NY, US
Keith N. Langston - Woodstock NY, US
Pak-kin Mak - Poughkeepsie NY, US
Chung-Lung K. Shum - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711118, 711119, 711144, 711146

Abstract:

Portions of data in a processor system are stored in a slower main memory and are transferred to a faster memory comprising a hierarchy of cache structures between one or more processors and the main memory. For a system with shared L2 cache(s) between the processor(s) and the main memory, an individual L1 cache of a processor must first communicate to an associated L2 cache(s), or check with such L2 cache(s), to obtain a copy of a particular line from a given cache location prior to, or upon modification, or appropriation of data at a given cached location. The individual L1 cache further includes provisions for notifying the L2 cache(s) upon determining when the data stored in the particular cache line in the L1 cache has been replaced, and when the particular cache line is disowned by an L1 cache, the L2 cache is updated to change the state of the particular cache line therein from an ownership state of exclusive to a particular identified CPU to an ownership state of exclusive to no CPU, thereby allowing reduction of cross interrogate delays during another processor acquisition of the same cache line.

US Patent:

7853635, Dec 14, 2010

Filed:

May 16, 2007

Appl. No.:

11/749224

Inventors:

Fadi Y. Busaba - Poughkeepsie NY, US
Steven R. Carlough - Poughkeepsie NY, US
David S. Hutton - Poughkeepsie NY, US
Christopher A. Krygowski - LaGrangeville NY, US
Sheryll H. Veneracion - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 7/38
G06F 7/52

US Classification:

708524, 708625

Abstract:

A system for binary multiplication in a superscalar processor includes a first pipeline, an execution unit, and a first multiplexer; a first rotator in communication with one register of the first pipeline and the execution unit; and a leading zero detection register in communication with the execution unit and another register of the first pipeline; a second pipeline, a second execution unit, and a second multiplexer; a rotator in communication with one register of the second pipeline and the second execution unit; and a leading zero detection register in communication with the second execution unit and another register of the first pipeline; and a third pipeline, a binary multiplier in communication with a pair registers of the third pipeline; a general register; an operand buffer for obtaining first and second operands; and a bus for communication between the pipelines, the general register and the operand buffer.

US Patent:

7861064, Dec 28, 2010

Filed:

Feb 26, 2008

Appl. No.:

12/037861

Inventors:

Khary J. Alexander - Poughkeepsie NY, US
Fadi Y. Busaba - Poughkeepsie NY, US
Bruce C. Giamei - Poughkeepsie NY, US
David S. Hutton - Tallahassee FL, US
Chung-Lung Kevin Shum - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/34
G06F 9/38

US Classification:

712214, 712219

Abstract:

A method for selectively accelerating early instruction processing including receiving an instruction data that is normally processed in an execution stage of a processor pipeline, wherein a configuration of the instruction data allows a processing of the instruction data to be accelerated from the execution stage to an address generation stage that occurs earlier in the processor pipeline than the execution stage, determining whether the instruction data can be dispatched to the address generation stage to be processed without being delayed due to an unavailability of a processing resource needed for the processing of the instruction data in the address generation stage, dispatching the instruction data to be processed in the address generation stage if it can be dispatched without being delayed due to the unavailability of the processing resource, and dispatching the instruction data to be processed in the execution stage if it can not be dispatched without being delayed due to the unavailability of the processing resource, wherein the processing of the instruction data is selectively accelerated using an address generation interlock scheme. A corresponding system and computer program product.

US Patent:

7975130, Jul 5, 2011

Filed:

Feb 20, 2008

Appl. No.:

12/034042

Inventors:

Khary J. Alexander - Poughkeepsie NY, US
Fadi Y. Busada - Poughkeepsie NY, US
Bruce C. Giamei - Poughkeepsie NY, US
David S. Hutton - Tallahassee FL, US
Chung-Lung Kevin Shum - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/312

US Classification:

712225, 712219

Abstract:

A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address information. The system also includes delay logic to monitor the instruction stream. The delay logic performs a method that includes detecting a load instruction following a store instruction in the instruction stream, comparing the operand address information of the store instruction with the load instruction. The method also includes delaying the load instruction in the processor pipeline in response to detecting a common field value between the operand address information of the store instruction and the load instruction.

US Patent:

8131945, Mar 6, 2012

Filed:

May 5, 2009

Appl. No.:

12/435468

Inventors:

David S. Hutton - Poughkeepsie NY, US
Kathryn M. Jackson - Poughkeepsie NY, US
Keith N. Langston - Woodstock NY, US
Pak-kin Mak - Poughkeepsie NY, US
Chung-Lung K. Shum - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711118, 711119, 711122, 711144, 711146

Abstract:

Caching where portions of data are stored in slower main memory and are transferred to faster memory between one or more processors and the main memory. The cache is such that an individual cache system must communicate to other associated cache systems, or check with such cache systems, to determine if they contain a copy of a given cached location prior to or upon modification or appropriation of data at a given cached location. The cache further includes provisions for determining when the data stored in a particular memory location may be replaced.