David Carl Kidd

US Patent:

20220270938, Aug 25, 2022

Filed:

Feb 19, 2021

Appl. No.:

17/180652

Inventors:

- San Diego CA, US
De LU - San Diego CA, US
Baldeo Sharan SHARMA - Bangalore, IN
Peeyush Kumar PARKAR - Bangalore, IN
Venkat NARAYANAN - San Diego CA, US
Rui LI - San Diego CA, US
Samy Shafik Tawfik ZAYNOUN - San Diego CA, US
Min CHEN - San Diego CA, US
David KIDD - San Diego CA, US
Amit PATIL - Bengaluru, IN

International Classification:

H01L 21/66
G06F 30/398

Abstract:

Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

US Patent:

20230022681, Jan 26, 2023

Filed:

Jul 22, 2021

Appl. No.:

17/383208

Inventors:

- San Diego CA, US
Luca MATTII - Cork City, IE
Gerard Patrick BALDWIN - Cork, IE
Angelo PINTO - San Diego CA, US
Satadru SARKAR - San Diego CA, US
David KIDD - San Diego CA, US
Ardavan MOASSESSI - San Diego CA, US
Paul PENZES - San Diego CA, US

International Classification:

H01L 27/02
H01L 27/118

Abstract:

In a first aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having a pitch that is uniform among the plurality of wrapped channels. In a second aspect, a semiconductor device includes a plurality of cells. Each cell of the plurality of cells includes four metal tracks running substantially parallel to each other in a first metal layer to provide signal routing and a plurality of wrapped channels having an asymmetric distribution. For example, a first distance between a first pair of adjacent wrapped channels is different than a second distance between a second pair of adjacent wrapped channels.

US Patent:

20180226401, Aug 9, 2018

Filed:

Mar 27, 2018

Appl. No.:

15/936724

Inventors:

- Kuwana, JP
David A. Kidd - San Diego CA, US

Assignee:

Mie Fujitsu Semiconductor Limited - Kuwana

International Classification:

H01L 27/088
H01L 29/78
G11C 7/06
G11C 7/08
H01L 29/10
H03K 3/356
H03K 5/06
H03L 7/08
H03L 7/081

Abstract:

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

US Patent:

20170117273, Apr 27, 2017

Filed:

Jan 4, 2017

Appl. No.:

15/398447

Inventors:

- Kuwana, JP
David A. Kidd - San Diego CA, US

International Classification:

H01L 27/088
H01L 29/78
H03L 7/08
G11C 7/06
H03K 5/06
H03K 3/356
G11C 7/08
H01L 29/10
H03L 7/081

Abstract:

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

US Patent:

20170076030, Mar 16, 2017

Filed:

Sep 11, 2015

Appl. No.:

14/852340

Inventors:

- San Diego CA, US
David Anthony KIDD - San Diego CA, US
Paul Ivan PENZES - San Diego CA, US

International Classification:

G06F 17/50

Abstract:

Techniques for power-density-based clock cell spacing and resulting integrated circuits (ICs) are disclosed herein. In one example, the techniques determine power-usage density for different types of clock cells, as power-usage density relates to heat and IR droop. With the power-usage density for each type of clock cell determined, the techniques assign a keep-out region for each type of clock cell that is not fixed for all types of clock cells. These regions are instead based on the heat and IR droop corresponding to estimated power-usage density for each type of clock cell. Clock cells are then placed in a layout of an IC. The resulting IC has clock cells spaced sufficiently to reduce heat and IR droop while concurrently having excellent timing closure and performance.

US Patent:

20160284698, Sep 29, 2016

Filed:

Jun 10, 2016

Appl. No.:

15/179370

Inventors:

- Kuwana, JP
David A. Kidd - San Diego CA, US

International Classification:

H01L 27/088
H01L 29/78
H03L 7/08
H03K 5/06
H03K 3/356
H01L 29/10
G11C 7/08

Abstract:

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.