David K Koh

US Patent:

7350172, Mar 25, 2008

Filed:

Dec 29, 2004

Appl. No.:

11/025747

Inventors:

David Koh - Boston MA, US
Zijad Galijasevic - Shrewsbury MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 17/50

US Classification:

716 7, 716 5

Abstract:

A method and system are described for generating a performance prediction report to assist finalizing a partitioning scheme of a block diagram model. Providing a user-defined partitioning scheme and information describing a target hardware platform used in that partitioning scheme, the present invention can generate a performance prediction report by analyzing the computational characteristics of the block diagram model.

US Patent:

7490032, Feb 10, 2009

Filed:

Dec 30, 2004

Appl. No.:

11/028172

Inventors:

David Koh - Boston MA, US
Mary Ann Nazario - Waltham MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 9/45

US Classification:

703 22, 707203

Abstract:

The present invention relates to integration of an external processor capable of execution of one or more functions into a block diagram model environment such that the block diagram model environment can make function calls directly into the external processor without the need for traditional wait loops or handshaking means. Furthermore the results of the function that was called in the external processor can be passed to the block diagram model environment from the external processor.

US Patent:

7523023, Apr 21, 2009

Filed:

Dec 23, 2004

Appl. No.:

11/021760

Inventors:

David Koh - Boston MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 17/50
G06F 3/023

US Classification:

703 2, 703 22, 717120, 717156

Abstract:

Method and systems are provided for representing interfaces between electronic components of a computational hardware device in a graphical model and automatically generating code from the graphical model to implement one or more component interfaces in the computational hardware device. A graphical modeling environment provides for the definition of interface boundaries to represent component interfaces between electronic components associated with partitions of a graphical model design. A code building tool automatically generates code from the graphical model to build executable instructions to run the component interfaces on the electronic components of the computational hardware device.

US Patent:

7584465, Sep 1, 2009

Filed:

Dec 20, 2004

Appl. No.:

11/019044

Inventors:

David Koh - Boston MA, US
Zijad Galijasevic - Shrewsbury MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 9/44
G06F 9/45

US Classification:

717162, 717113, 717151, 717159, 717109

Abstract:

Methods and systems are provided for automatically generating code from a graphical model representing a design to be implemented on components of a target computational hardware device. During the automatic code generating process, a memory mapping is automatically determined and generated to provide an optimization of execution of the program on the target device. The optimized memory mapping is incorporated into building the program executable from the automatically generated code of the graphical model.

US Patent:

8156481, Apr 10, 2012

Filed:

Oct 5, 2007

Appl. No.:

11/868112

Inventors:

David Koh - Boston MA, US
Murat Belge - Chelmsford MA, US
Pieter J. Mosterman - Framingham MA, US

Assignee:

The Mathworks, Inc. - Natick MA

International Classification:

G06F 9/45

US Classification:

717151, 717152, 717153, 717154, 717158

Abstract:

A device generates code with a technical computing environment (TCE) based on a model and information associated with a target processor, registers an algorithm with the TCE, automatically sets optimization parameters applied during generation of the code based on the algorithm, executes the generated code, receives feedback based on execution of the generated code, and uses the feedback to automatically update the optimization parameters and to automatically regenerate the code with the TCE until an optimal code is achieved for the target processor.

US Patent:

8180964, May 15, 2012

Filed:

Sep 28, 2007

Appl. No.:

11/864590

Inventors:

David Koh - Boston MA, US
Murat Belge - Chelmsford MA, US
James K. Weixel - Ashland MA, US

Assignee:

The Mathworks, Inc. - Natick MA

International Classification:

G06F 12/00

US Classification:

711118

Abstract:

A system generates application code based on a received model, determines an optimal cache configuration based on the application code, executes the application code in a target cache environment, generates cache performance results based on the executed application code, and re-determines the optimal cache configuration based on the cache performance results.

US Patent:

8219378, Jul 10, 2012

Filed:

Sep 28, 2007

Appl. No.:

11/864475

Inventors:

David Koh - Boston MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 9/44

US Classification:

703 21, 703 20

Abstract:

A system receives a model, internals associated with a target processor, and code information associated with the target processor, and obtains a bit-true model simulation for the target processor based on the model, the target processor internals, and the target processor code information.

US Patent:

8230395, Jul 24, 2012

Filed:

Jul 21, 2009

Appl. No.:

12/506621

Inventors:

David Koh - Boston MA, US
Zijad Galijasevic - Shrewsbury MA, US

Assignee:

The MathWorks, Inc. - Natick MA

International Classification:

G06F 9/44
G06F 9/45

US Classification:

717121, 717131, 717153, 717159

Abstract:

Methods and systems are provided for automatically generating code from a graphical model representing a design to be implemented on components of a target computational hardware device. During the automatic code generating process, a memory mapping is automatically determined and generated to provide an optimization of execution of the program on the target device. The optimized memory mapping is incorporated into building the program executable from the automatically generated code of the graphical model.