David A Korn

US Patent:

6576939, Jun 10, 2003

Filed:

Jan 10, 2000

Appl. No.:

09/480072

Inventors:

Terry Gilton - Boise ID
David Korn - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2976

US Classification:

257288, 257286, 257297, 257327, 438233, 438299, 438586, 438597

Abstract:

In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover.

US Patent:

6713355, Mar 30, 2004

Filed:

May 8, 2003

Appl. No.:

10/431822

Inventors:

Terry Gilton - Boise ID
David Korn - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21336

US Classification:

438279, 438301, 438303

Abstract:

In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers. In yet another implementation, a transistor comprises a semiconductive substrate and a gate stack formed thereover.

US Patent:

6838365, Jan 4, 2005

Filed:

Dec 15, 2003

Appl. No.:

10/736805

Inventors:

Terry Gilton - Boise ID, US
David Korn - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 213205
H01L 21336
H01L 2976

US Classification:

438585, 438197, 257213, 257368

Abstract:

A method of forming an electronic component includes forming first and second conductive materials over a substrate, with the second material having a higher oxidation rate than an oxidation rate of the first material when exposed to a thermal oxidizing atmosphere. The first and second conductive materials are first etched to form a conductive component. The conductive component has opposing outer lateral edges of the first and second conductive materials which span between the opposing outer lateral edges. Second etching is conducted into both of the second material outer lateral edges to recess them inside of the first material outer lateral edges. After the second etching, the substrate is exposed to the thermal oxidizing atmosphere effective to grow an oxide layer over both of the outer lateral edges of the first and second conductive materials. Electronic components are disclosed and claimed independent of any method of manufacture.

US Patent:

7537804, May 26, 2009

Filed:

Apr 28, 2006

Appl. No.:

11/413466

Inventors:

Noel Rocklein - Boise ID, US
John Vernon - Boise ID, US
Jeff Nelson - Boise ID, US
F. Daniel Gealy - Boise ID, US
David Korn - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

C23C 16/455

US Classification:

42725531, 42725532

Abstract:

In some embodiments, the invention may include utilization of at least one iteration of an ALD pulse sequence that has the pulse subsets M-M-R- and M-(R-M-): where x is at least 2; where Mis a first metal-containing precursor comprising a first metal, Mis a second metal-containing precursor comprising a second metal different from the first metal, and R is a reactant which reacts with one or both of the first and second metals. The ALD pulse sequence forms material over a substrate, and such material includes the first and second metals. The hyphen between pulses means that the second pulse directly follows the first pulse, with the term “directly follows” indicating that the second pulse either immediately follows the first pulse or that only a purge separates the first and second pulses.

US Patent:

8049304, Nov 1, 2011

Filed:

Apr 13, 2009

Appl. No.:

12/422788

Inventors:

Noel Rocklein - Boise ID, US
John Vernon - Boise ID, US
Jeff Nelson - Boise ID, US
F. Daniel Gealy - Boise ID, US
David Korn - Boise ID, US

Assignee:

Round Rock Research, LLC - Mt. Kisco NY

International Classification:

H01L 29/92

US Classification:

257532, 257E29343

Abstract:

The invention includes ALD-type methods in which two or more different precursors are utilized with one or more reactants to form a material. In particular aspects, the precursors are hafnium and aluminum, the only reactant is ozone, and the material is hafnium oxide predominantly in a tetragonal crystalline phase.

US Patent:

8299462, Oct 30, 2012

Filed:

Oct 25, 2011

Appl. No.:

13/280556

Inventors:

Noel Rocklein - Boise ID, US
John Vernon - Boise ID, US
Jeff Nelson - Boise ID, US
F. Daniel Gealy - Boise ID, US
David Korn - Boise ID, US

Assignee:

Round Rock Research, LLC - Mt. Kisco NY

International Classification:

H01L 29/12

US Classification:

257 43, 257410, 257E29108

Abstract:

The invention includes a dielectric mode from ALD-type methods in which two or more different precursors are utilized with one or more reactants to form the dielectric material. In particular aspects, the precursors are aluminum and hafnium and/or zirconium for materials made from a hafnium precursor, the hafnium oxide is predominantly in a tetragonal crystalline phase.

US Patent:

57883041, Aug 4, 1998

Filed:

May 17, 1996

Appl. No.:

8/649224

Inventors:

David Korn - Boise ID
Keith Smith - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B65D 8586

US Classification:

294159

Abstract:

A wafer carrier for use in the transportation and storage of semiconductor wafers. More particularly, the invention is a wafer carrier having both a rigid structure and a corrosion resistant coating. The wafer carrier includes a unitary frame having several wafer supports joined by connecting members. The frame is coated with a material, such as a fluoropolymer, which is resistant to corrosive materials typically used in semiconductor fabrication processes.

US Patent:

60928514, Jul 25, 2000

Filed:

Nov 15, 1999

Appl. No.:

9/440839

Inventors:

David Korn - Boise ID
Keith Smith - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

B65D 8586

US Classification:

294159

Abstract:

A wafer carrier for use in the transportation and storage of semiconductor wafers. More particularly, the invention is a wafer carrier having both a rigid structure and a corrosion resistant coating. The wafer carrier includes a unitary frame having several wafer supports joined by connecting members. The frame is coated with a material, such as a fluoropolymer, which is resistant to corrosive materials typically used in semiconductor fabrication processes.