David L Larkin

US Patent:

6350673, Feb 26, 2002

Filed:

Aug 12, 1999

Appl. No.:

09/373215

Inventors:

David L. Larkin - Richardson TX
George E. Harris - Garland TX
William D. Smith - Garland TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438622, 438624, 438631, 438958

Abstract:

A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device ( ) having at least one metal layer ( ) completed. Then, a planarizing dielectric layer ( ) is added to the semiconductor device ( ). The semiconductor device ( ) is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device ( ).

US Patent:

7413947, Aug 19, 2008

Filed:

Jan 17, 2006

Appl. No.:

11/333222

Inventors:

David L. Larkin - Richardson TX, US
Ashish V. Gokhale - Allen TX, US
Dhaval A. Saraiya - Allen TX, US
Quang Xuan Mai - Sugar Lane TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8234

US Classification:

438238, 438240, 438257, 438258, 438261, 438275, 257E21008

Abstract:

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer ( or ). The integrated high voltage capacitor further includes a second capacitor plate () located over the insulator () and a top-level dielectric layer () located at least partially along a sidewall of the second capacitor plate ().

US Patent:

7470991, Dec 30, 2008

Filed:

Oct 13, 2005

Appl. No.:

11/250047

Inventors:

David L. Larkin - Richardson TX, US
Lily X. Springer - Dallas TX, US
Makoto Takemura - Dallas TX, US
Ashish V. Gokhale - Allen TX, US
Dhaval A. Saraiya - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/48
H01L 23/52
H01L 29/40

US Classification:

257764, 257199, 257532, 257296, 257E21008, 257E21122, 438238, 438240, 438257, 438381

Abstract:

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or ). The integrated high voltage capacitor further includes capacitance uniformity structures () located at least partially within the insulator () and a second capacitor plate () located over the insulator ().

US Patent:

7755400, Jul 13, 2010

Filed:

May 29, 2008

Appl. No.:

12/129075

Inventors:

Ricky Dale Jordanger - Allen TX, US
David Leonard Larkin - Richardson TX, US
David Wayne Stout - Lewisville TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03L 7/00

US Classification:

327142, 327306, 327531

Abstract:

Systems and methods for digital isolation in circuits are provided. On power-up in an isolation application, there may be multiple power supplies. For example, one for an input side and one for an output side, both in relation to an isolation barrier. Upon power up, the input and output may not be at the same state. The bias of the output may be the opposite of what is on the input. An isolator solution is provided which integrates the digital isolation into the analog solution. A DC signal corresponds to the static state of the data at start-up and an AC signal is generated when switching begins. In one example, the output level corresponds to the input level when the steady state information is encoded and sent across as an AC signal.

US Patent:

8114731, Feb 14, 2012

Filed:

Nov 24, 2008

Appl. No.:

12/276507

Inventors:

David L. Larkin - Richardson TX, US
Lily X. Springer - Dallas TX, US
Makoto Takemura - Dallas TX, US
Ashish V. Gokhale - Allen TX, US
Dhaval A. Saraiya - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8244

US Classification:

438238, 438250, 438381, 257E21008

Abstract:

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or ). The integrated high voltage capacitor further includes capacitance uniformity structures () located at least partially within the insulator () and a second capacitor plate () located over the insulator ().

US Patent:

8273623, Sep 25, 2012

Filed:

Feb 14, 2012

Appl. No.:

13/396159

Inventors:

David L. Larkin - Richardson TX, US
Lily X. Springer - Dallas TX, US
Makoto Takemura - Dallas TX, US
Ashish V. Gokhale - Allen TX, US
Dhaval A. Saraiya - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8242

US Classification:

438239, 438250, 438394, 257E21008

Abstract:

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or ). The integrated high voltage capacitor further includes capacitance uniformity structures () located at least partially within the insulator () and a second capacitor plate () located over the insulator ().

US Patent:

20020030247, Mar 14, 2002

Filed:

Nov 20, 2001

Appl. No.:

09/988651

Inventors:

David Larkin - Richardson TX, US
George Harris - Garland TX, US
William Smith - Garland TX, US

International Classification:

H01L023/58
H01L029/792

US Classification:

257/629000, 257/634000, 257/635000, 438/958000, 257/324000

Abstract:

A method for decreasing CHC degradation is provided. The method includes providing a semiconductor device () having at least one metal layer () completed. Then, a planarizing dielectric layer () is added to the semiconductor device (). The semiconductor device () is heated in a hydrogen rich environment until hydrogen completely saturates the semiconductor device ().

US Patent:

20060186450, Aug 24, 2006

Filed:

Oct 13, 2005

Appl. No.:

11/249535

Inventors:

David Larkin - Richardson TX, US
Lily Springer - Dallas TX, US
Makoto Takemura - Dallas TX, US
Ashish Gokhale - Allen TX, US
Dhaval Saraiya - Allen TX, US

Assignee:

Texas Instruments Inc. - Dallas TX

International Classification:

H01L 29/94

US Classification:

257306000

Abstract:

The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate () located over or in a semiconductor substrate (), and an insulator () located over the first capacitor plate (), at least a portion of the insulator () comprising an interlevel dielectric layer (, or ). The integrated high voltage capacitor further includes a second capacitor plate () located over the insulator ().