David Lovelace

US Patent:

6487395, Nov 26, 2002

Filed:

Mar 16, 1998

Appl. No.:

09/039502

Inventors:

Jeffrey C. Durec - Chandler AZ
David Kevin Lovelace - Chandler AZ
Mark D. Randol - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04Q 720

US Classification:

455 78, 455 83

Abstract:

A radio frequency (RF) switch ( ) for use in a wireless communication system operated in a time delay division mode of operation. The switch includes a pair of PIN diodes ( and ) serially coupled between the transmitter and receiver paths of the communication system which share a common node ( ) to which a bias voltage is provided. The bias voltage is switched between first and second voltage levels to alternately cause one and the other of the pin diodes to be forward biased while the other is reversed bias. In this manner the transmitter and receiver paths will be alternately shorted to alternating current ground while the other path is shorted to a common node to an antenna.

US Patent:

6819196, Nov 16, 2004

Filed:

Feb 13, 2003

Appl. No.:

10/366177

Inventors:

David K. Lovelace - Chandler AZ
Klaas Wortel - Phoenix AZ

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

H03B 532

US Classification:

331183, 331158, 331 16

Abstract:

An oscillator circuit. In one embodiment, the oscillator includes a gain circuit, an envelope detector, and an amplitude comparison circuit. The trans-conductance circuit is configured to amplify a periodic signal produced by a crystal. Amplitude peaks of the periodic signal may be detected in the envelope detector, which may determine an average amplitude value based on the detected peaks. The average amplitude value may be compared to a DC voltage value in an amplitude comparison circuit. The DC voltage value may include both a DC average of the periodic signal as well as a predetermined DC offset value. The gain circuit may adjust the level of amplification of the periodic signal based on a feedback signal in order to ensure that the oscillator produces a periodic output signal at a desired level so as to insure oscillation and the minimum use of current to achieve oscillations.

US Patent:

7055047, May 30, 2006

Filed:

Apr 9, 2003

Appl. No.:

10/410089

Inventors:

Klaas Wortel - Phoenix AZ, US
David K. Lovelace - Chandler AZ, US
Luis J. Briones - Chandler AZ, US

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

G06F 1/32

US Classification:

713320, 713300

Abstract:

Detecting a radio frequency (RF) environment around a computer and using a power management scheme for an RF user input device being used by the computer system. If the computer system is in a single user environment, a power management scheme may be used to conserve power on the RF user input device. If the computer system is in a multi-user environment, a power management scheme may be used to minimize interference between neighboring computer systems by minimizing the signal strength of the RF signal from the RF user input device and the RF signal from the computer system.

US Patent:

7415260, Aug 19, 2008

Filed:

Mar 8, 2004

Appl. No.:

10/795740

Inventors:

Troy L. Stockstad - Chandler AZ, US
Klaas Wortel - Phoenix AZ, US
Luis J. Briones - Chandler AZ, US
David Lovelace - Austin TX, US

Assignee:

Standard Microsystems Corporation - Hauppauge NY

International Classification:

H04B 1/00

US Classification:

455312, 455324

Abstract:

A current-mode direct conversion RF receiver is presented. In one set of embodiments the RF receiver comprises a simple transconductor input stage to create a current-mode modulated signal from a voltage-mode modulated signal. A downconversion mixer may be coupled to the transconductor input stage via a low impedance current cascode stage, and may operate to create a set of current-mode quadrature baseband signals from the current-mode modulated signal. The downconversion mixer may be implemented with a transistor-switching network, which may be driven by a phase locked loop (PLL) with quadrature outputs. The set of current-mode quadrature baseband signals may be converted back to the voltage domain by a transimpedance filter, which may perform channel selection for the receiver. The transimpedance filter may additionally include a low frequency zero to remove DC offsets. The receiver may be implemented using CMOS design technologies and operated with minimal self-mixing effects, minimal DC offset in the baseband signal, and utilizing low voltages.

US Patent:

56592639, Aug 19, 1997

Filed:

Mar 25, 1996

Appl. No.:

8/622536

Inventors:

Stephen W. Dow - Chandler AZ
David K. Lovelace - Chandler AZ
Jeffrey C. Durec - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 744

US Classification:

327356

Abstract:

A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

US Patent:

61378526, Oct 24, 2000

Filed:

Dec 23, 1997

Appl. No.:

8/996903

Inventors:

Michael McGinn - Tempe AZ
David Kevin Lovelace - Chandler AZ

Assignee:

Motorola, Inc - Schaumburg IL

International Classification:

H03D 324

US Classification:

375375

Abstract:

An image reject receiver (10) uses a mixer circuit (12) and a mixer circuit (16) to frequency translate an incoming reference signal (RF. sub. IN) and generate a first output signal (V. sub. OUT1) and a second output signal (V. sub. OUT2), respectively. Two phase detectors (26 and 36) measure a phase difference between the first and second output signals (V. sub. OUT1, and V. sub. OUT2) and a difference circuit (30) provides a difference value in accordance with the phase difference. The difference value cancels any phase shift due to time delays associated with the phase detectors (26 and 36). The difference value is fed back to a phase shift circuit (20) for adjusting the phase of the second output signal (V. sub. OUT2) and locking the first output signal (V. sub. OUT1) in-phase with the second output signal (V. sub. OUT2).

US Patent:

56170564, Apr 1, 1997

Filed:

Jul 5, 1995

Appl. No.:

8/498038

Inventors:

William E. Main - Mesa AZ
David K. Lovelace - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G05F 110

US Classification:

327538

Abstract:

A base current compensation circuit (10) generates a current that tracks a gain of a transistor (11). The compensation circuit (10) includes a current mirror formed by a mirror transistor (12) and an output transistor (14). The mirror transistor (12) is connected to the transistor (11) whose gain is tracked. A current source (16) and a feedback transistor (13) causes the mirror transistor (12) to draw a base current from the transistor (11) so that a collector current of the transistor (11) matches a reference current. The output transistor (14) amplifies the base current of the transistor (11) to generate the tracking current in the collector electrode of the output transistor (14).

US Patent:

6177832, Jan 23, 2001

Filed:

Jul 6, 1998

Appl. No.:

9/110289

Inventors:

Jeffrey C. Durec - Chandler AZ
David Kevin Lovelace - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 304

US Classification:

327563

Abstract:

A differential to single-ended converter which combines a pair of applied differential signals of a given frequency applied into a single-ended signal supplied to an output thereof, including capacitive means (14,16 or 36) coupled across a pair of terminals to which the differential signals are applied and transmission line circuitry (18, or 38, 40) coupled across the capacitive means for shifting the phase of one of the differential signals applied to one of the pair of terminals such that it is in phase with the other one of the differential signals applied at the other of the pair of terminals wherein said signals are combined into a single-ended signal and applied to an output of the converter.