David William Matula

US Patent:

6782405, Aug 24, 2004

Filed:

Jun 7, 2001

Appl. No.:

09/876786

Inventors:

David W. Matula - Dallas TX
Cristina S. Iordache - Beaverton OR

Assignee:

Southern Methodist University - Dallas TX

International Classification:

G06F 744

US Classification:

708504, 708654

Abstract:

The division and square root systems include a multiplier. The systems also include a multipartite table system, a folding inverter, and a complement inverter, each coupled to the multiplier. The division and square root functions can be performed using three scaling iterations. The system first determines both a first and a second scaling value. The first scaling value is a semi-complement term computed using the folding inverter to invert selected bits of the input. The second scaling value is a table lookup value obtained from the multipartite table system. In the first iteration, the system scales the input by the semi-complement term. In the second iteration, the resulting approximation is scaled by a function of the table lookup value. In the third iteration, the approximation is scaled by a value obtained from a function of the semi-complement term and the table lookup value. After the third iteration, the approximation is available for rounding.

US Patent:

6938062, Aug 30, 2005

Filed:

Mar 26, 2002

Appl. No.:

10/107598

Inventors:

David W. Matula - Dallas TX, US
Willard S. Briggs - Boulder CO, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F007/38

US Classification:

708235, 708272

Abstract:

An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recorded output values directly to partial product generators of a multiplier unit is also disclosed.

US Patent:

6978289, Dec 20, 2005

Filed:

Mar 26, 2002

Appl. No.:

10/108251

Inventors:

David W. Matula - Dallas TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F007/38

US Classification:

708551, 708270

Abstract:

An apparatus and method are disclosed for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials. Unlike prior art methods that individually round each polynomial coefficient of a function, the method of the present invention use a “ripple carry” rounding method to round each coefficient using information from the previously rounded coefficient. The “ripple carry” method generates rounded coefficients that significantly improve the total rounding error for the function.

US Patent:

7194498, Mar 20, 2007

Filed:

Feb 25, 2002

Appl. No.:

10/080707

Inventors:

David William Matula - Dallas TX, US
Peter-Michael Seidel - Dallas TX, US
Lee D. McFearin - Plano TX, US

Assignee:

Southern Methodist University - Dallas TX

International Classification:

G06F 7/52

US Classification:

708620, 708501, 708624

Abstract:

A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor.

US Patent:

7346642, Mar 18, 2008

Filed:

Nov 14, 2003

Appl. No.:

10/714554

Inventors:

Willard S. Briggs - Boulder CO, US
David W. Matula - Dallas TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 7/38

US Classification:

708497, 708500, 708605

Abstract:

Methods for determining the square root, reciprocal square root, or reciprocal of a number performed by a processor of a computer system. The methods produce high precision estimates without using iterative steps. In addition, the methods taught herein utilize compressed tables for the coefficient terms A, B, and C from the quadratic expression Ax+Bx+C, thus minimizing hardware requirements.

US Patent:

7543008, Jun 2, 2009

Filed:

Apr 27, 2005

Appl. No.:

11/115616

Inventors:

David W. Matula - Dallas TX, US
Willard S. Briggs - Boulder CO, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/02
G06F 7/38

US Classification:

708272, 708493, 708628

Abstract:

An apparatus and method are disclosed for providing higher radix redundant digit lookup tables for digital lookup table circuits. A compressed direct lookup table unit accesses a redundant digits lookup table that is capable of providing a high order part and a low order part that can be directly concatenated to form an output numeric value. The redundant digits lookup table of the invention is structured so that no output overflow exceptions are created. A redundant digits lookup table recoder capable of providing recoded output values directly to partial product generators of a multiplier unit is also disclosed.

US Patent:

7962537, Jun 14, 2011

Filed:

Jun 26, 2007

Appl. No.:

11/768742

Inventors:

David W. Matula - Dallas TX, US
Mitchell A. Thornton - Dallas TX, US
Lun Li - Santa Clara CA, US

Assignee:

Southern Methodist University - Dallas TX

International Classification:

G06F 7/00

US Classification:

708200

Abstract:

Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.

US Patent:

8060550, Nov 15, 2011

Filed:

Sep 27, 2006

Appl. No.:

11/535607

Inventors:

David W. Matula - Dallas TX, US

Assignee:

Southern Methodist University - Dallas TX

International Classification:

G06F 1/02
G06F 7/00
G06F 7/38
G06F 15/00

US Classification:

708517, 708277, 708491, 708492

Abstract:

Transforming an integer comprises receiving the integer, where the integer can be expressed as a modular factorization. The modular factorization comprises one or more factors, where each factor has an exponent. The integer is expressed as a product of residues. A discrete logarithm of the integer is established from a sum corresponding to the product of residues. A value for an exponent of a factor is determined from the discrete logarithm. The integer is represented as the modular factorization comprising the one or more factors, where each factor has a value for the exponent.