David W Mcclure

US Patent:

6347381, Feb 12, 2002

Filed:

Oct 30, 1998

Appl. No.:

09/183491

Inventors:

David C. McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

G06F 1130

US Classification:

714 30, 714721

Abstract:

A detection circuit and a test mode circuit incorporating the detection circuit is disclosed. The detection circuit includes an N-channel transistor having a first source, a first gate, and a first drain, wherein the first drain is connected to a supply voltage. The detection circuit also includes a P-channel transistor having a second source, a second gate, and a second drain, wherein the second source is connected to the first source and the second drain provides an output signal indicative of a supervoltage being applied to the first gate. The test mode circuit also includes a memory access cycle time-out feature override circuit.

US Patent:

6359819, Mar 19, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/751007

Inventors:

David C. McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc.. - Carrollton TX

International Classification:

G11C 700

US Classification:

365201, 365145

Abstract:

A circuit and method for performing a stress test on a ferroelectric memory device. The memory device includes a memory cell array having a plurality of row lines, column lines and plate lines. The memory device further includes test circuitry for receiving at least one test control signal and in response to the at least one test control signal allowing a voltage differential to be applied between the column lines and the plate lines, so that a stress voltage may be applied across each of the memory cells at one time.

US Patent:

6365991, Apr 2, 2002

Filed:

Nov 29, 1999

Appl. No.:

09/450108

Inventors:

Tom Youssef - Dallas TX
David Charles McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H02J 904

US Classification:

307 66, 307 64, 307 80, 307 85, 324763

Abstract:

A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device. An external control signal provided to the device ensures that the test mode remains enabled, thereby inhibiting the device from exiting the test mode and switching to the secondary power supply in a normal operating mode.

US Patent:

6456519, Sep 24, 2002

Filed:

Dec 29, 2000

Appl. No.:

09/752209

Inventors:

David C. McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

G11C 1122

US Classification:

365145, 365 65, 36523006, 36523008, 365233

Abstract:

A circuit and method are disclosed for asynchronously accessing accessing a ferroelectric memory device. The ferroelectric memory device internally generates timing signals for latching a received address signal and driving the row lines of the device based upon transitions appearing on the received address signal. The circuit receives an address signal and asserts an edge detect signal in response. The address signal is latched following the edge detect a signal being asserted. Address decode circuitry receives the latched address and generates decoded output signals that identify a row of memory cells to be accessed. In this way, a ferroelectric memory device may effectively replace an asynchronous static random access random access memory (SRAM) device.

US Patent:

6476669, Nov 5, 2002

Filed:

Jul 10, 2001

Appl. No.:

09/902206

Inventors:

David C. McClure - Carrollton TX
Rong Yin - Coppell TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H03K 1772

US Classification:

327543

Abstract:

A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistors gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit.

US Patent:

6486007, Nov 26, 2002

Filed:

Jul 20, 2001

Appl. No.:

09/910396

Inventors:

Tsiu Chiu Chan - Carrollton TX
Mehdi Zamanian - Carrollton TX
David Charles McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

H01L 21335

US Classification:

438142, 438199, 438229, 438305, 365154, 365156, 257 59, 257 66

Abstract:

A method is disclosed for a memory cell for a static random access memory. The memory cell includes a pair of cross-coupled CMOS logic inverters that are connected together to form a latch, and a pair of p-channel transmission gate transistors that are connected to the logic inverters for selectively providing access to the latch. The layout of the memory cell includes a rectangular active area in which the p-channel transistors of the memory cell are located. The rectangular active area abuts a similar active area of an adjacent memory cell along a row of memory cells so as to form a single rectangular active area for the p-channel memory cell transistors. The rectangular active area reduces the occurrence of fabrication-related phenomena that adversely effect the performance of the memory cell.

US Patent:

6496439, Dec 17, 2002

Filed:

Jun 29, 2001

Appl. No.:

09/895491

Inventors:

David C. McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

G11C 514

US Classification:

365229, 365 49, 365227, 365228, 365226, 36518907, 36518909, 365195, 365 51

Abstract:

A content addressable memory (CAM) includes a voltage power supply input and an enable input. An enable control circuit is connected to the enable input, and operates to compare an external voltage to an enable reference voltage. If the external voltage drops below the enable reference voltage, the enable control circuit drives the enable input to place the CAM into a low current, stand-by mode of operation. A voltage supply back-up circuit is connected to the voltage power supply input, and operates to compare the external voltage to a supply reference voltage. If the external voltage drops below the supply reference voltage, the voltage supply back-up circuit switches the voltage power supply input for the CAM from the external voltage input to a battery back-up. As an alternative, the voltage power supply input for the CAM includes a separate power input for a CAM array, and the switch causes only that separate power input for the CAM array to be powered from the battery back-up. The foregoing circuits are fabricated on an integrated circuit chip with the CAM.

US Patent:

6518746, Feb 11, 2003

Filed:

Aug 17, 2001

Appl. No.:

09/931820

Inventors:

David Charles McClure - Carrollton TX

Assignee:

STMicroelectronics, Inc. - Carrollton TX

International Classification:

G01R 3128

US Classification:

3241581, 324760

Abstract:

An integrated circuit structure provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The test mode structure of the IC memory device has a number of bipolar transistors, a number of ETD transistors coupled to the bipolar transistors, and a logic element coupled to the bipolar and ETD transistors at a node. The ETD transistors operate to ensure that the emitter of corresponding bipolar transistors have a voltage of Vb-Vbe.