David M Mccracken

US Patent:

6339812, Jan 15, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/410139

Inventors:

David E. McCracken - San Francisco CA
Martin M. Deneroff - Palo Alto CA
Gregory M. Thorson - Altoona WI
John S. Keen - Mountain View CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

711141, 711144, 711145, 711148, 712 1, 712 28

Abstract:

A node controller ( ) in a computer system ( ) includes a processor interface unit ( ), a memory directory interface unit ( ), and a local block unit ( ). In response to a memory location in a memory ( ) associated with the memory directory interface unit ( ) being altered, the processor interface unit ( ) generates an invalidation request for transfer to the memory directory interface unit ( ). The memory directory interface unit ( ) provides the invalidation request and identities of processors ( ) affected by the invalidation request to the local block unit ( ). The local block unit ( ) determines which ones of the identified processors ( ) are present in the computer system ( ) and generates an invalidation message for each present processor ( ) for transfer thereto. Each of the present processors ( ) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit ( ) that generated the invalidation request. The local block unit ( ) determines which ones of the identified processors ( ) are not present in the computer system ( ) and generates an acknowledgment message for each non-existent processor ( ).

US Patent:

6381681, Apr 30, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/410120

Inventors:

David E. McCracken - San Francisco CA
Allan James Christie - Fremont CA
James A. Stuart Fiske - Palo Alto CA

Assignee:

Silicon Graphics, Inc. - Mountianview CA

International Classification:

G06F 1200

US Classification:

711152, 711153

Abstract:

A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer ( ) having a plurality of processor regions and a plurality of memory pages ( ). Each processor region includes one or more processors ( ). Each processor ( ) includes a cache ( ), and each memory page ( ) includes one or more cache lines ( ) for coupling to the cache ( ) of processors ( ) within the plurality of processor regions using the memory page ( ). Each memory page ( ) includes a set of protection bits ( ) associated with each processor region in the plurality of processor regions. The set of protection bits ( ) includes an acquire protection bit ( ) for each processor region in the plurality of processor regions. The acquire protection bit ( ) determines whether the associated processor is enabled to perform acquire operations on the memory page ( ). The set of protection bits ( ) also includes a release protection bit ( ) for each processor region in the plurality of processor regions.

US Patent:

6453408, Sep 17, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409606

Inventors:

James A. Stuart Fiske - Palo Alto CA
David Edward McCracken - San Francisco CA
Leonard Mark Widra - Saratoga CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1516

US Classification:

712 29, 709216, 711141, 711145, 711152, 711219

Abstract:

A method for controlling memory page migration in a parallel processor computer ( ) is provided that comprises requesting access to a memory page ( ) by a requester processor ( ). The method then determines whether the requester processor ( ) is a local processor or a remote processor. The method then increments a local access counter ( ) and identifies the local access counter ( ) as an incremented counter in response to determining that the requester processor ( ) is a local processor. If the requester processor ( ) is determined to be a remote processor, the method increments a remote access counter ( ) and identifies the remote access counter ( ) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold ( ) or if a difference between the local access counter ( ) and the remote access counter ( ) exceeds a difference threshold ( ). The method then generates a system interrupt in response to a positive threshold processing indicator.

US Patent:

6487685, Nov 26, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409607

Inventors:

James A. Stuart Fiske - Palo Alto CA
David E. McCracken - San Francisco CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1100

US Classification:

714701, 774779, 774785, 36518503

Abstract:

A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation. The method then populates unused bits in the common data representation with default values that are chosen to provide known values for any ECC bits that are only needed for larger data formats thereby minimizing the number of ECC bits stored in each of the plurality of data formats. Errors are detected and corrected in the common data representation.

US Patent:

6532501, Mar 11, 2003

Filed:

Sep 30, 1999

Appl. No.:

09/409605

Inventors:

David E. McCracken - San Francisco CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

710 52, 710 39, 710 54, 710 56, 710112, 710309, 710263, 710310

Abstract:

A system and method for distributing output queue space is provided that includes an output queue ( ), a input queue ( ), an asynchronous input queue ( ), and a credit allocation module ( ). The output queue ( ) has a certain number of output spaces ( ) where each output space ( ) represents an output queue credit. The output queue ( ) releases output queue credits when releasing data from output spaces ( ) and receives data in response to a command being processed from the input queue ( ). The input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The asynchronous input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits.

US Patent:

6578115, Jun 10, 2003

Filed:

Jan 14, 2002

Appl. No.:

10/047347

Inventors:

David E. McCracken - San Francisco CA
Martin M. Deneroff - Palo Alto CA
Gregory M. Thorson - Altoona WI
John S. Keen - Mountain View CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

711144, 711141, 711145, 711148, 712 1, 712 28

Abstract:

A node controller ( ) in a computer system ( ) includes a processor interface unit ( ), a memory directory interface unit ( ), and a local block unit ( ). In response to a memory location in a memory ( ) associated with the memory directory interface unit ( ) being altered, the processor interface unit ( ) generates an invalidation request for transfer to the memory directory interface unit ( ). The memory directory interface unit ( ) provides the invalidation request and identities of processors ( ) affected by the invalidation request to the local block unit ( ). The local block unit ( ) determines which ones of the identified processors ( ) are present in the computer system ( ) and generates an invalidation message for each present processor ( ) for transfer thereto. Each of the present processors ( ) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit ( ) that generated the invalidation request. The local block unit ( ) determines which ones of the identified processors ( ) are not present in the computer system ( ) and generates an acknowledgment message for each non-existent processor ( ).

US Patent:

6751698, Jun 15, 2004

Filed:

Sep 29, 1999

Appl. No.:

09/407428

Inventors:

Martin M. Deneroff - Palo Alto CA
Givargis G. Kaldani - San Jose CA
Yuval Koren - San Francisco CA
David Edward McCracken - San Francisco CA
Swami Venkataraman - San Jose CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

710317

Abstract:

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data.

US Patent:

7406086, Jul 29, 2008

Filed:

Jun 15, 2004

Appl. No.:

10/868181

Inventors:

Martin M. Deneroff - Palo Alto CA, US
Givargis G. Kaldani - San Jose CA, US
Yuval Koren - San Francisco CA, US
David Edward McCracken - San Francisco CA, US
Swami Venkataraman - San Jose CA, US

Assignee:

Silicon Graphics, Inc. - Sunnyvale CA

International Classification:

H04L 12/56

US Classification:

370400, 710317

Abstract:

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data.