David Bruce Mccracken

US Patent:

6339812, Jan 15, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/410139

Inventors:

David E. McCracken - San Francisco CA
Martin M. Deneroff - Palo Alto CA
Gregory M. Thorson - Altoona WI
John S. Keen - Mountain View CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

711141, 711144, 711145, 711148, 712 1, 712 28

Abstract:

A node controller ( ) in a computer system ( ) includes a processor interface unit ( ), a memory directory interface unit ( ), and a local block unit ( ). In response to a memory location in a memory ( ) associated with the memory directory interface unit ( ) being altered, the processor interface unit ( ) generates an invalidation request for transfer to the memory directory interface unit ( ). The memory directory interface unit ( ) provides the invalidation request and identities of processors ( ) affected by the invalidation request to the local block unit ( ). The local block unit ( ) determines which ones of the identified processors ( ) are present in the computer system ( ) and generates an invalidation message for each present processor ( ) for transfer thereto. Each of the present processors ( ) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit ( ) that generated the invalidation request. The local block unit ( ) determines which ones of the identified processors ( ) are not present in the computer system ( ) and generates an acknowledgment message for each non-existent processor ( ).

US Patent:

6381681, Apr 30, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/410120

Inventors:

David E. McCracken - San Francisco CA
Allan James Christie - Fremont CA
James A. Stuart Fiske - Palo Alto CA

Assignee:

Silicon Graphics, Inc. - Mountianview CA

International Classification:

G06F 1200

US Classification:

711152, 711153

Abstract:

A memory protection system for shared memory in a multiprocessor computer is provided that comprises a multiprocessor computer ( ) having a plurality of processor regions and a plurality of memory pages ( ). Each processor region includes one or more processors ( ). Each processor ( ) includes a cache ( ), and each memory page ( ) includes one or more cache lines ( ) for coupling to the cache ( ) of processors ( ) within the plurality of processor regions using the memory page ( ). Each memory page ( ) includes a set of protection bits ( ) associated with each processor region in the plurality of processor regions. The set of protection bits ( ) includes an acquire protection bit ( ) for each processor region in the plurality of processor regions. The acquire protection bit ( ) determines whether the associated processor is enabled to perform acquire operations on the memory page ( ). The set of protection bits ( ) also includes a release protection bit ( ) for each processor region in the plurality of processor regions.

US Patent:

6532501, Mar 11, 2003

Filed:

Sep 30, 1999

Appl. No.:

09/409605

Inventors:

David E. McCracken - San Francisco CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

710 52, 710 39, 710 54, 710 56, 710112, 710309, 710263, 710310

Abstract:

A system and method for distributing output queue space is provided that includes an output queue ( ), a input queue ( ), an asynchronous input queue ( ), and a credit allocation module ( ). The output queue ( ) has a certain number of output spaces ( ) where each output space ( ) represents an output queue credit. The output queue ( ) releases output queue credits when releasing data from output spaces ( ) and receives data in response to a command being processed from the input queue ( ). The input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits. The asynchronous input queue ( ) queues commands and requests a number of output queue credits in response to receiving a command. The asynchronous input queue ( ) also releases the queued commands for processing in response to receiving the requested number of output queue credits.

US Patent:

6578115, Jun 10, 2003

Filed:

Jan 14, 2002

Appl. No.:

10/047347

Inventors:

David E. McCracken - San Francisco CA
Martin M. Deneroff - Palo Alto CA
Gregory M. Thorson - Altoona WI
John S. Keen - Mountain View CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1208

US Classification:

711144, 711141, 711145, 711148, 712 1, 712 28

Abstract:

A node controller ( ) in a computer system ( ) includes a processor interface unit ( ), a memory directory interface unit ( ), and a local block unit ( ). In response to a memory location in a memory ( ) associated with the memory directory interface unit ( ) being altered, the processor interface unit ( ) generates an invalidation request for transfer to the memory directory interface unit ( ). The memory directory interface unit ( ) provides the invalidation request and identities of processors ( ) affected by the invalidation request to the local block unit ( ). The local block unit ( ) determines which ones of the identified processors ( ) are present in the computer system ( ) and generates an invalidation message for each present processor ( ) for transfer thereto. Each of the present processors ( ) process their invalidation message and generate an acknowledgment message for transfer to the processor interface unit ( ) that generated the invalidation request. The local block unit ( ) determines which ones of the identified processors ( ) are not present in the computer system ( ) and generates an acknowledgment message for each non-existent processor ( ).

US Patent:

62790730, Aug 21, 2001

Filed:

Sep 30, 1999

Appl. No.:

9/410137

Inventors:

David E. McCracken - San Francisco CA
David L. McCall - Eau Claire WI

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1200

US Classification:

711105

Abstract:

A configurable synchronizer (10) for DDR-SDRAM (12) is provided that includes a strobe select module (40) operable to receive a memory select signal (106) and to pass strobe signals (20, 30) from one or more DDR-SDRAMs (16, 18) to a number of synchronizer circuits (44) corresponding to data signals (17) passed in parallel by each DDR-SDRAM as indicated by the memory select signal (106). A rising edge latch (174) receives a rising edge data signal (170) and latches the rising edge data signal (170) through the rising edge latch (174) on a rising edge of the strobe signal (152). A falling edge latch (176) receives a falling edge data signal (172) and latches the falling edge data signal (172) through the falling edge latch (176) on a falling edge of the strobe signal (152). A data signal selector (180) receives a data order control signal (195) and forwards the rising edge data signal (170) from the rising edge latch (174) to an intermediate output (196) on either a rising edge of a memory clock cycle (193) or a falling edge of a memory clock cycle (193) followed by forwarding the falling edge data signal (172) from the falling edge latch (176) to the intermediate output (196) on an opposite edge of the memory clock cycle (193) in response to the data order control signal (195). An output latch (202) receives the intermediate output (196) and latches the intermediate output (196) through the output latch (202) to an output signal (154) on each core clock cycle (190).

US Patent:

45075760, Mar 26, 1985

Filed:

Oct 28, 1982

Appl. No.:

6/437248

Inventors:

David R. McCracken - Portland OR
Robin R. Larson - Aloha OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H03K 512
H03K 19092

US Classification:

307475

Abstract:

A special purpose pulse amplifier with programmable high and low levels for complex IC testing is disclosed. Its output has independently programmable positive and negative transition rates and is reverse terminated in 50 ohms. It also has the ability to be switched to a high resistance, low capacitance output state. This circuit is the interface between a complex, computer controlled system of timing and pattern generation hardware, and an integrated circuit to be tested. This device has reduced waveform aberrations, lower inhibited capacitance, low input to output delay for reducing timing error, programmable signal transition rates, and the amplitude range and transition rate control to accommodate all the important device technologies expected in high pin-count parts.