David A Mccracken

US Patent:

6453408, Sep 17, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409606

Inventors:

James A. Stuart Fiske - Palo Alto CA
David Edward McCracken - San Francisco CA
Leonard Mark Widra - Saratoga CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1516

US Classification:

712 29, 709216, 711141, 711145, 711152, 711219

Abstract:

A method for controlling memory page migration in a parallel processor computer ( ) is provided that comprises requesting access to a memory page ( ) by a requester processor ( ). The method then determines whether the requester processor ( ) is a local processor or a remote processor. The method then increments a local access counter ( ) and identifies the local access counter ( ) as an incremented counter in response to determining that the requester processor ( ) is a local processor. If the requester processor ( ) is determined to be a remote processor, the method increments a remote access counter ( ) and identifies the remote access counter ( ) as the incremented counter. The method next sets a threshold processing indicator to a positive value if the incremented counter exceeds a value threshold ( ) or if a difference between the local access counter ( ) and the remote access counter ( ) exceeds a difference threshold ( ). The method then generates a system interrupt in response to a positive threshold processing indicator.

US Patent:

6487685, Nov 26, 2002

Filed:

Sep 30, 1999

Appl. No.:

09/409607

Inventors:

James A. Stuart Fiske - Palo Alto CA
David E. McCracken - San Francisco CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1100

US Classification:

714701, 774779, 774785, 36518503

Abstract:

A method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats and creating a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry having one of the plurality of data formats and formats the data entry into the common data representation. The method then populates unused bits in the common data representation with default values that are chosen to provide known values for any ECC bits that are only needed for larger data formats thereby minimizing the number of ECC bits stored in each of the plurality of data formats. Errors are detected and corrected in the common data representation.

US Patent:

6751698, Jun 15, 2004

Filed:

Sep 29, 1999

Appl. No.:

09/407428

Inventors:

Martin M. Deneroff - Palo Alto CA
Givargis G. Kaldani - San Jose CA
Yuval Koren - San Francisco CA
David Edward McCracken - San Francisco CA
Swami Venkataraman - San Jose CA

Assignee:

Silicon Graphics, Inc. - Mountain View CA

International Classification:

G06F 1300

US Classification:

710317

Abstract:

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data.

US Patent:

7406086, Jul 29, 2008

Filed:

Jun 15, 2004

Appl. No.:

10/868181

Inventors:

Martin M. Deneroff - Palo Alto CA, US
Givargis G. Kaldani - San Jose CA, US
Yuval Koren - San Francisco CA, US
David Edward McCracken - San Francisco CA, US
Swami Venkataraman - San Jose CA, US

Assignee:

Silicon Graphics, Inc. - Sunnyvale CA

International Classification:

H04L 12/56

US Classification:

370400, 710317

Abstract:

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory/directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data.

US Patent:

7881321, Feb 1, 2011

Filed:

Jul 28, 2008

Appl. No.:

12/181202

Inventors:

Martin M. Deneroff - Palo Alto CA, US
Givargis G. Kaldani - Los Gatos CA, US
Yuval Koren - San Francisco CA, US
David Edward McCracken - San Francisco CA, US

Assignee:

Silicon Graphics International - Fremont CA

International Classification:

H04L 12/56
H04J 3/22
G06F 13/00

US Classification:

370412, 370413, 370465, 710317

Abstract:

A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

US Patent:

8447910, May 21, 2013

Filed:

Nov 30, 2010

Appl. No.:

12/956568

Inventors:

Seung Baek Yi - San Diego CA, US
David Edward McCracken - San Jose CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 13/00

US Classification:

710315, 455 412

Abstract:

This disclosure involves methods and systems for providing a host with a Bluetooth transceiver by way of a virtual USB connection to a PCI/PCIe bus in which the virtual USB connection is controlled by a modified OHCI. The Bluetooth transceiver is configured to send a status signal when there is data to be transferred to the host. The modified OHCI is configured to activate a list processor upon receipt of the status signal, such that the list processor controls the transfer of the data to be transferred to the host. After delivery of the data to the host, the modified OHCI is configured to inactivate the list processor. Further, the modified OHCI is configured to be compatible with standard USB software resident on the host.

US Patent:

8493357, Jul 23, 2013

Filed:

Mar 4, 2011

Appl. No.:

13/041173

Inventors:

David McCracken - Aptos CA, US

Assignee:

Integrated Device Technology, Inc - San Jose CA

International Classification:

G06F 3/045

US Classification:

345174, 345179

Abstract:

Method and apparatus for providing haptic feedback in connection with a capacitive sensing mechanism are described. In one embodiment, the apparatus comprises a convex, non-metallic structure arranged so as to maintain physical separation between an activator and the capacitive sensing mechanism until sufficient force is applied by the activator. The structure does not form a part of an electrical circuit comprising the capacitive sensing mechanism.

US Patent:

20120306802, Dec 6, 2012

Filed:

Jun 6, 2011

Appl. No.:

13/154227

Inventors:

David Harold McCracken - Aptos CA, US

International Classification:

G06F 3/045

US Classification:

345174, 178 1806

Abstract:

A touch sensor is provided. The touch sensor includes at least two capacitive sensing electrodes, each of the at least two capacitive sensing electrodes having a surface area that is smaller than an area of a touch from a user. The at least two capacitive sensing electrodes each include a substrate, a single conductive element formed on the substrate, and electronic circuitry coupled to the at least two capacitive sensing electrodes for measuring a self-capacitance of the at least two capacitive sensing electrodes. A position corresponding to the touch of a user is determined by the electronic circuitry based on a difference of the measured self-capacitance between the at least two capacitive sensing electrodes.