David Louis Mccracken

US Patent:

20060109750, May 25, 2006

Filed:

Nov 11, 2005

Appl. No.:

11/271178

Inventors:

Michael McCracken - Nashville TN, US
Shirley McCracken - Nashville TN, US
David McCracken - Nashville TN, US

International Classification:

G04B 23/02
G08B 1/00

US Classification:

368244000, 340309160

Abstract:

An electronic reminder, the alert feature of which uses visual and/or audible alert signals, with customizable surface areas. The surface areas include an area onto which a distributor of the reminder can apply information specific to a known end user or user group. A surface area of the housing also permits a purchaser of relatively small quantities of the invention to apply their own promotional information prior to redistribution to their customers. Another area of the housing includes a surface area of such material as to allow the end user to handwrite information associated with the reminding function, such as the storage location and brand name (or product type) of a particular item, or a task. A display device permits a user-defined, reminder-related visual cue (for example, a photograph) to be held in place and displayed. Additionally, the reminder may include a heart-shaped lens that illuminates when the alert occurs, flashing (and/or sounding) in the familiar rhythm of a human heartbeat to call attention to information about which the user is being reminded.

US Patent:

45075760, Mar 26, 1985

Filed:

Oct 28, 1982

Appl. No.:

6/437248

Inventors:

David R. McCracken - Portland OR
Robin R. Larson - Aloha OR

Assignee:

Tektronix, Inc. - Beaverton OR

International Classification:

H03K 512
H03K 19092

US Classification:

307475

Abstract:

A special purpose pulse amplifier with programmable high and low levels for complex IC testing is disclosed. Its output has independently programmable positive and negative transition rates and is reverse terminated in 50 ohms. It also has the ability to be switched to a high resistance, low capacitance output state. This circuit is the interface between a complex, computer controlled system of timing and pattern generation hardware, and an integrated circuit to be tested. This device has reduced waveform aberrations, lower inhibited capacitance, low input to output delay for reducing timing error, programmable signal transition rates, and the amplitude range and transition rate control to accommodate all the important device technologies expected in high pin-count parts.