David W Mcelroy

US Patent:

53134273, May 17, 1994

Filed:

Sep 20, 1991

Appl. No.:

7/763105

Inventors:

John F. Schreck - Houston TX
David J. McElroy - Allen TX
Pradeep L. Shah - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1606
G11C 1134

US Classification:

365218

Abstract:

A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.

US Patent:

51517604, Sep 29, 1992

Filed:

Jul 30, 1991

Appl. No.:

7/738004

Inventors:

Manzur Gill - Rosharon TX
David J. McElroy - Lubbock TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2968
H01L 2702

US Classification:

357 235

Abstract:

According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and the second conductor (16) is capacitively coupled to third conductor (22).

US Patent:

43331670, Jun 1, 1982

Filed:

Oct 5, 1979

Appl. No.:

6/082371

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700
G11C 1140

US Classification:

365222

Abstract:

A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.

US Patent:

45077576, Mar 26, 1985

Filed:

Mar 23, 1982

Appl. No.:

6/361009

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1700

US Classification:

365104

Abstract:

A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used in a memory array of the PROM type. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.

US Patent:

42824460, Aug 4, 1981

Filed:

Oct 1, 1979

Appl. No.:

6/080712

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 500
G11C 1140
H01L 2978
H01L 2702

US Classification:

3072385

Abstract:

A floating gate type electrically programmable memory device is made by an N-channel double-level polysilicon self-aligned process which results in a very dense array. The programming inefficiency caused by inherent resistance of elongated diffused regions used as column lines is overcome by a capacitive discharge programming method. Distributed capacitance of the column lines is charged to the programming voltage before the selected row line is brought to a high voltage, producing a pulse of current through the cell. A series of these programming pulses may be used.

US Patent:

51777053, Jan 5, 1993

Filed:

Sep 5, 1989

Appl. No.:

7/402399

Inventors:

David J. McElroy - Rosenberg TX
Sebastiano D'Arrigo - Houston TX
Manzur Gill - Rosharon TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700
G11C 1600

US Classification:

365185

Abstract:

A method is described for programming an array of EEPROM cells. Programming occurs through a Fowler-Nordheim tunnel window (34) between a source bitline (24) and a floating gate conductor (42) of a selected cell. The voltages applied to the control gate and to the source are selected to differ sufficiently to cause electrons to be drawn through the tunnel window (34) from the source region (24) to the floating gate conductor (42). The non-selected bitlines have a voltage impressed thereon that is of sufficient value to prevent inadvertent programming of cells in the selected row. The non-selected wordlines (48) have a voltage impressed thereon that is of sufficient value to prevent erasing of programmed non-selected cells.

US Patent:

41510208, Apr 24, 1979

Filed:

Jan 26, 1977

Appl. No.:

5/762612

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21225
H01L 2126

US Classification:

148187

Abstract:

An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

US Patent:

51107538, May 5, 1992

Filed:

Sep 4, 1990

Appl. No.:

7/576887

Inventors:

Manzur Gill - Rosharon TX
David J. McElroy - Rosenberg TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170
H01L 2700

US Classification:

437 52

Abstract:

A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between wordlines and between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of progammable memory cells.