David R Mcelroy

US Patent:

6456535, Sep 24, 2002

Filed:

Jun 15, 2001

Appl. No.:

09/882920

Inventors:

Leonard Forbes - Corvallis OR
Luan C. Tran - Meridian ID
Alan R. Reinberg - Westport CT
Joseph E. Geusic - Berkeley Heights NJ
Kie Y. Ahn - Chappaqua NY
Paul A. Farrar - So. Burlington VT
Eugene H. Cloud - Boise ID
David J. McElroy - Livingston TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518528, 36518526, 36518514

Abstract:

Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms ( ). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10 Coulombs at for at least 1.

US Patent:

62494600, Jun 19, 2001

Filed:

Feb 28, 2000

Appl. No.:

9/513938

Inventors:

Leonard Forbes - Corvallis OR
Luan C. Tran - Meridian ID
Alan R. Reinberg - Westport CT
Joseph E. Geusic - Berkeley Heights NJ
Kie Y. Ahn - Chappaqua NY
Paul A. Farrar - So. Burlington VT
Eugene H. Cloud - Boise ID
David J. McElroy - Livingston TX

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518528

Abstract:

Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (. ANG. ). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10. sup.