David Lee Mcelroy

US Patent:

51517604, Sep 29, 1992

Filed:

Jul 30, 1991

Appl. No.:

7/738004

Inventors:

Manzur Gill - Rosharon TX
David J. McElroy - Lubbock TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2968
H01L 2702

US Classification:

357 235

Abstract:

According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and the second conductor (16) is capacitively coupled to third conductor (22).

US Patent:

52873153, Feb 15, 1994

Filed:

May 7, 1993

Appl. No.:

8/057435

Inventors:

John F. Schreck - Houston TX
Debra J. Dolby - Sugarland TX
David J. McElroy - Lubbock TX
Eddie H. Breashears - Lubbock TX
John H. MacPeak - Lubbock TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 702
G11C 1134

US Classification:

365210

Abstract:

A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.

US Patent:

50574469, Oct 15, 1991

Filed:

Aug 6, 1990

Appl. No.:

7/563369

Inventors:

Manzur Gill - Rosharon TX
David J. McElroy - Lubbock TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21265

US Classification:

437 43

Abstract:

According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).

US Patent:

53134320, May 17, 1994

Filed:

Nov 12, 1991

Appl. No.:

7/790122

Inventors:

John F. Schreck - Houston TX
Phat C. Truong - Houston TX
David J. McElroy - Lubbock TX
Harvey J. Stiegler - Houston TX
Benjamin H. Ashmore - Houston TX
Manzur Gill - Arcola TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1606
G11C 1604

US Classification:

36523006

Abstract:

A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.

US Patent:

55232493, Jun 4, 1996

Filed:

Dec 23, 1994

Appl. No.:

8/364529

Inventors:

Manzur Gill - Arcola TX
David J. McElroy - Lubbock TX
Inn K. Lee - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 218247

US Classification:

437 43

Abstract:

An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). The memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) through the tunnel window (13a) to the source-line (17 ). The program and erase regions of the cells are physically separate from each other, and the characteristics, including the oxides, of each of those regions may be made optimum independently from each other.