David M Mcelroy

US Patent:

60494832, Apr 11, 2000

Filed:

Aug 3, 1999

Appl. No.:

9/368453

Inventors:

John F. Schreck - Lucas TX
David J. McElroy - Allen TX
Brian W. Huber - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1614

US Classification:

36518527

Abstract:

Circuits for applying a programming voltage and erase voltage to memory cells in a nonvolatile memory device are disclosed. The reverse breakdown of p-n junctions within the memory cells is prevented by providing a clamping p-n junction in the path used to apply the program or erase voltage to the memory cells. The clamping p-n junction will breakdown before the p-n junctions within the memory cells, protecting the memory cells from the adverse effects of a reverse breakdown condition.

US Patent:

56417012, Jun 24, 1997

Filed:

Mar 30, 1995

Appl. No.:

8/413291

Inventors:

Hideyuki Fukuhara - Ami-machi, JP
Yoichi Miyai - Toride, JP
David J. McElroy - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2170
H01L 2700

US Classification:

438 6

Abstract:

A method for fabricating a semiconductor device includes the steps of: forming fuses (40) and conductive pads (46) above a semiconductor substrate (43); depositing a layer of cap oxide (44) over the fuses and the conductive pads; sintering the cap oxide; etching back the layer of cap oxide until the top surface of an insulator (42) over the fuses and the top surfaces of the conductive pads are exposed; performing electrical tests (48) by way of the conductive pads; trimming (50) at least a part of the fuses with a laser beam; depositing a silicon nitride layer (52) overall; depositing a mask coating over the silicon nitride; patterning the mask coating (54) to expose the conductive pads; and etching the mask coating and the silicon nitride layer to expose the conductive pads.

US Patent:

54126037, May 2, 1995

Filed:

May 6, 1994

Appl. No.:

8/239008

Inventors:

John F. Schreck - Lucas TX
Cetin Kaya - Dallas TX
David J. McElroy - Allen TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700

US Classification:

36518901

Abstract:

The drain-to-source voltage and current for programming a selected nonvolatile memory cell 10 are achieved efficiently by pumping the source 11 of a selected cell 11 to a voltage less than the voltage VSS at the reference-voltage terminal of the memory cell array while, at the same time, pumping the drain 12 of the selected cell 10 to a voltage greater than the voltage VCC, which may be 3 V, at the supply-voltage terminal of the memory cell array. The cell substrate W2 is pumped to a voltage close to the voltage of the source 11 and, optionally, below the voltage of the source 11. One or more simple charge-pump circuits convert the output of the voltage supply VCC to a source-drain voltage and current capable of programming the selected nonvolatile cell 10 by hot carrier injection.