David J Mcelroy

US Patent:

53134273, May 17, 1994

Filed:

Sep 20, 1991

Appl. No.:

7/763105

Inventors:

John F. Schreck - Houston TX
David J. McElroy - Allen TX
Pradeep L. Shah - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1606
G11C 1134

US Classification:

365218

Abstract:

A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.

US Patent:

43331670, Jun 1, 1982

Filed:

Oct 5, 1979

Appl. No.:

6/082371

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 700
G11C 1140

US Classification:

365222

Abstract:

A semiconductor device comprises an array of rows and columns of dynamic-type memory cells with on-chip refresh circuitry which automatically produces a refresh operation invisible to the CPU. The refresh circuitry includes an address counter and a multiplexer to insert the refresh address when an internal clock indicates a refresh cycle. The refresh address counter is incremented after each refresh cycle. If a refresh command is being executed when an address presented, the refresh operation is completed then the device is accessed in the usual manner. By specifying the access time of the device as the sum of the usual access type plus the time needed for refresh, the internal refresh is invisible to the CPU.

US Patent:

45077576, Mar 26, 1985

Filed:

Mar 23, 1982

Appl. No.:

6/361009

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 1700

US Classification:

365104

Abstract:

A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used in a memory array of the PROM type. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.

US Patent:

42824460, Aug 4, 1981

Filed:

Oct 1, 1979

Appl. No.:

6/080712

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 500
G11C 1140
H01L 2978
H01L 2702

US Classification:

3072385

Abstract:

A floating gate type electrically programmable memory device is made by an N-channel double-level polysilicon self-aligned process which results in a very dense array. The programming inefficiency caused by inherent resistance of elongated diffused regions used as column lines is overcome by a capacitive discharge programming method. Distributed capacitance of the column lines is charged to the programming voltage before the selected row line is brought to a high voltage, producing a pulse of current through the cell. A series of these programming pulses may be used.

US Patent:

41510208, Apr 24, 1979

Filed:

Jan 26, 1977

Appl. No.:

5/762612

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21225
H01L 2126

US Classification:

148187

Abstract:

An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

US Patent:

43366473, Jun 29, 1982

Filed:

Dec 21, 1979

Appl. No.:

6/106126

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21425
G11C 1140

US Classification:

29571

Abstract:

An MOS read only memory or ROM formed by the standard N-channel silicon gate manufacturing process uses a cell structure which allows implant programming after the metal level of contacts and interconnections has been deposited and patterned. Address lines and gates are polysilicon strips and output and ground lines are metal strips perpendicular to the address lines; these metal strips make contact to the sources and drains defined by N+ regions. Each potential MOS transistor in the array is programmed to be a logic "1" or "0" by selective ion implant through the polysilicon gates and thin gate oxide, using photoresist as a mask, after application of the metal level. The ion implant is not required to penetrate through the metal lines.

US Patent:

41157052, Sep 19, 1978

Filed:

Jun 14, 1976

Appl. No.:

5/695886

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 1760

US Classification:

307140

Abstract:

An electronic calculator with a power supply ON-OFF arrangement actuated by momentary-closure push-button switches which are part of the keyboard. A bistable latch circuit on the calculator chip is continuously powered by the battery, and is caused to flip to an ON condition by actuating an ON key, and this turns on a large, low-resistance transistor which is in series with the voltage supply line going to all of the other electronic circuitry on the chip.

US Patent:

46087516, Sep 2, 1986

Filed:

Aug 7, 1984

Appl. No.:

6/638442

Inventors:

David J. McElroy - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2704
H01L 2978

US Classification:

29576B

Abstract:

A dynamic read/write memory cell of the one transistor type is made by a single-level polysilicon process in which the word lines and the gates of the access transistors are formed by the metal strips. No metal-to-silicon or metal-to-polysilicon contacts are needed. The access transistors are made by etching through polysilicon strips which are the capacitor bias plates. The size of the transistor is not determined by alignment accuracy.