David W Noble

US Patent:

8286392, Oct 16, 2012

Filed:

Jun 19, 2009

Appl. No.:

13/057132

Inventors:

David Noble - Pasadena CA, US
James Chuda - Los Angeles CA, US

International Classification:

E04H 1/04

US Classification:

52 794, 526521

Abstract:

An inhabitable space frame () can define and support inhabitable living space within, around and projecting from the exterior of the perimeter of the space frame (). The space frame () includes a vector matrix of strut members () that defines a plurality of interconnected basic tetrahedral modules () and, optionally, a plurality of prime octahedral modules (). At least a part of each prime octahedral module () in the plurality of prime octahedral modules () is adjacent to at least two of the basic tetrahedral modules (). Use of one or more right triangular faces, or planes, within a repeating geometry of a vector matrix enables an interior of the space frame () to be inhabitable, with horizontal floors and vertical walls aligned with associated strut members ().

US Patent:

50844113, Jan 28, 1992

Filed:

Nov 29, 1988

Appl. No.:

7/277593

Inventors:

Stephen Laderman - Menlo Park CA
Martin Scott - San Francisco CA
Theodore I. Kamins - Palo Alto CA
Judy L. Hoyt - Palo Alto CA
Clifford A. King - Palo Alto CA
James F. Gibbons - Palo Alto CA
David B. Noble - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2120

US Classification:

437131

Abstract:

Improved devices with silicon to SiGe alloy heterojunctions are provided for in accordance with the following discoveries. X-ray topography and transmission electron microscopy were used to quantify misfit-dislocation spacings in as-grown Si. sub. 1-x Ge. sub. x films formed by Limited Reaction Processing (LRP), which is a chemical vapor deposition technique. These analysis techniques were also used to study dislocation formation during annealing of material grown by both LRP and by molecular beam epitaxy (MBE). The thickness at which misfit dislocations first appear in as-grown material was similar for both growth techniques. The thermal stability of capped and uncapped films was also investigated after rapid thermal annealing in the range of 625. degree. to 1000. degree. C. Significantly fewer misfit dislocations were observed in samples containing an epitaxial silicon cap. Some differences in the number of misfit dislocations generated in CVD and MBE films were observed after annealing uncapped layers at temperatures between 625. degree. and 825. degree. C.

US Patent:

52565505, Oct 26, 1993

Filed:

Jun 12, 1991

Appl. No.:

7/715054

Inventors:

Stephen Laderman - Menlo Park CA
Martin Scott - San Francisco CA
Theodore I. Kamins - Palo Alto CA
Judy L. Hoyt - Palo Alto CA
Clifford A. King - Palo Alto CA
James F. Gibbons - Palo Alto CA
David B. Noble - Sunnyvale CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 21205

US Classification:

437106

Abstract:

The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer. The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth.

US Patent:

52022846, Apr 13, 1993

Filed:

Dec 1, 1989

Appl. No.:

7/444464

Inventors:

Theodore I. Kamins - Palo Alto CA
David B. Noble - Sunnyvale CA
Judy L. Hoyt - Palo Alto CA
James F. Gibbons - Palo Alto CA
Martin P. Scott - San Francisco CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01L 2120
H01L 21205

US Classification:

437 89

Abstract:

Several methods are disclosed for minimizing the number of defects or misfit locations in a SiGe layer selectively or non-selectively deposited on a partially oxide masked Si substrate.