David Wayne Norris

US Patent:

7088835, Aug 8, 2006

Filed:

Jul 6, 1999

Appl. No.:

09/352659

Inventors:

David Norris - Austin TX, US
David N. Suggs - Austin TX, US

Assignee:

Legerity, Inc. - Austin TX

International Classification:

H03G 3/00

US Classification:

381107, 381104, 700 94

Abstract:

A digital wavetable audio synthesizer is described. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can ad LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators.

US Patent:

48051390, Feb 14, 1989

Filed:

Oct 22, 1987

Appl. No.:

7/111476

Inventors:

David Norris - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 700
G11C 1900
G11C 1928

US Classification:

365 78

Abstract:

A propagating first-in, first-out (FIFO) storage device is driven by a two-phase non-overlapping clock and includes a plurality of storage cells (C1,. . . C4) and a plurality of tracking bit cell circuits (T1,. . . T4). Each of the storage cells includes first pass gate transistors (G1,. . . G8), first inverters (INV1,. . . INV8), second pass gate transistors (G9,. . . G16), and second inverters (INV9,. . . INV16). The first pass gate transistors are responsive to a control signal from the tracking circuit for loading data input signals into the first inverter means. The second pass gate transistors are responsive to a first phase of the clock for shifting the data input signals into the second inverters.

US Patent:

61191949, Sep 12, 2000

Filed:

Mar 19, 1998

Appl. No.:

9/044750

Inventors:

Paul Miranda - Austin TX
Larry Hewitt - Austin TX
David Norris - Austin TX
James Bunnell - LaFayette CO

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1300

US Classification:

710129

Abstract:

A USB host controller provides transaction type status signals indicating USB activity type. The status signals include a bulk status bit signal indicative of bulk activity on a USB, a control status bit signal indicative of control activity on the USB, an isochronous status bit signal indicative of isochronous activity on the USB and an interrupt status bit signal indicative of an acknowledged interrupt on the USB. In addition a programmable mask register is provided for masking any or all of the status bits. The status bits may be combined and provided as a single signal indicative of USB activity.

US Patent:

55348440, Jul 9, 1996

Filed:

Apr 3, 1995

Appl. No.:

8/415266

Inventors:

David Norris - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 702

US Classification:

3401462

Abstract:

A static-type comparator, which compares the magnitude of a first binary number with a second binary number and determines if the first binary number is equal to, greater than, or less than the second binary number, is described. The comparator comprises a carry chain of comparison cells. Each comparison cell in the carry chain compares the magnitude of a different bit position of the first number with a corresponding bit position in the second number. The comparison cells input a first voltage signal, representing a binary value of a bit position of the first number, and a second voltage signal, representing a binary value of a corresponding bit position of the second number. A voltage signal from a voltage source Vcc is input into the carry chain and propagates through the chain until a comparison cell detects that there is a difference in magnitudes for a particular bit position. If a difference in magnitudes is detected, the comparison cell will output a voltage signal indicating whether the first number is greater than or less than the second number. If the numbers are equal, voltage signal Vcc propagates through the entire carry chain and is output.

US Patent:

60470739, Apr 4, 2000

Filed:

Nov 2, 1994

Appl. No.:

8/334462

Inventors:

David Norris - Austin TX
David N. Suggs - Austin TX

Assignee:

Advanced Micro Devices, Inc. - DE

International Classification:

H03G 300

US Classification:

381 61

Abstract:

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44. 1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field.

US Patent:

56758081, Oct 7, 1997

Filed:

Nov 2, 1994

Appl. No.:

8/333537

Inventors:

Dele E. Gulick - Austin TX
Larry D. Hewitt - Austin TX
Michael Hogan - Austin TX
David Norris - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 132

US Classification:

395750

Abstract:

A power control and memory refresh rate management circuit is described. The power control circuit provides circuitry for selectively disabling or enabling modular logic circuit blocks within a VLSI integrated circuit under program control from an external processor, or for suspended circuit operation in general. In low-power modes external memory refresh signal generation circuits are provided with a low-frequency oscillator signal to conserve power.

US Patent:

56683383, Sep 16, 1997

Filed:

Nov 2, 1994

Appl. No.:

8/333564

Inventors:

Larry D. Hewitt - Austin TX
David N. Suggs - Austin TX
David Norris - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G10H 102
G10H 700

US Classification:

84629

Abstract:

A digital wavetable audio synthesizer with an LFO generator is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator's addressing rate controls the pitch of the synthesizer's output signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice's volume, for creating a tremolo effect. The LFO generator assigns two triangular-wave LFOs to each of the 32 possible voices. One LFO is dedicated to vibrato (frequency modulation) effects and the other to tremolo (amplitude modulation) effects.

US Patent:

60580666, May 2, 2000

Filed:

Sep 25, 1998

Appl. No.:

9/160992

Inventors:

David E. Norris - Austin TX
Larry D. Hewitt - Austin TX
Jeffrey M. Blumenthal - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 800

US Classification:

36523005

Abstract:

A register array accessible by both a system microprocessor and a digital signal processor of a PC audio circuit, comprising: (i) a random access memory (RAM) having a first port connected to a digital signal processor input/output port, and a second port connected to a RAM input/output port; (ii) a register data port connected to the RAM input/output port and having a connection to a register data bus; (iii) timing circuitry for timing the register array operations; (iv) row and column select circuitry for respectively selecting rows and columns in said RAM; and (v) an input/output channel ready signal line connected to said timing circuitry. The RAM includes a plurality of edge bits each of which stores a value indicating whether processing of a row of data values stored in said RAM is active or inactive. The system microprocessor is disabled from accessing the RAM whenever the RAM is not idle or the microprocessor seeks to access a row of the RAM currently subject to access by the digital signal processor. If the microprocessor is disabled from writing data to the RAM, the data may be temporarily stored in the register data port until the microprocessor's access is enabled.

Address:

2606 W 48 St, Austin, TX 78731

Phone:

5127841590

VIN:

JTEEW21A470040191

Make:

TOYOTA

Model:

HIGHLANDER HYBRID

Year:

2007