David W Patrick

US Patent:

47362936, Apr 5, 1988

Filed:

Apr 11, 1984

Appl. No.:

6/599644

Inventors:

David M. Patrick - Aurora IL

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G06F 1300

US Classification:

364200

Abstract:

In a processing system (10) comprising a main memory (102) for storing blocks (150) of four contiguous words (160) of information, a cache memory (101) for storing selected ones of the blocks, and a two-word wide bus (110) for transferring words from the main memory to the cache, the cache memory is implemented in two memory parts (301, 302) as a two-way interleaved two-way set-associative memory. One memory part implements odd words of one cache set (0), and even words of the other cache set (1), while the other memory part implements even words of the one cache set and odd words of the other cache set. Storage locations (303) of the memory parts are grouped into at least four levels (204) with each level having a location from each of the memory parts and each of the cache sets. The cache receives a block over the bus in two pairs of contiguous words. The cache memory is updated with both words of a word pair simultaneously.